JP3031040B2 - Manufacturing method of integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a method for manufacturing an integrated circuit including an internal cell requiring a clock.

[0002]

2. Description of the Related Art Conventionally, as an integrated circuit provided with an internal cell requiring a clock, there is known an integrated circuit having a logic diagram of a clock wiring, that is, a clock logic diagram shown in FIG.

In FIG. 1, reference numeral 1 denotes a clock input terminal to which a clock is externally input, 2 denotes an input clock buffer cell for taking in the clock input to the clock input terminal 1, and 3 denotes an internal cell requiring a clock. This integrated circuit is provided by the input clock buffer cell 2
This is to drive all the internal cells 3 that require a clock.

In recent years, however, integrated circuits have been equipped with a large number of internal cells 3 requiring clocks in response to demands for larger scale and higher speed. For this reason,
As shown in FIG. 5, when all of the internal cells 3 requiring a clock are driven only by the input clock buffer cell 2, a problem occurs in that the clock skew increases.

In view of the above, a clock logic diagram shown in FIG. 6 has been proposed. In this integrated circuit, clock skew is reduced by arranging a plurality of internal clock buffer cells 4 between an input clock buffer cell 2 and an internal cell 3 requiring a clock.

[0006]

However, in this integrated circuit, the problem of assigning (assigning) which internal cell 3 to which internal clock buffer cell 4 must be dealt with by the user himself. There is a problem in that if the number is large, the burden on the user becomes too heavy.

At the stage of logic design, since it is not known where the internal cell 3 is located on the chip, for example, as shown in FIG.
Medium, for example, the internal clock buffer cell 4A and the internal cell 3 assigned to the internal clock buffer cell 4A
In the middle, for example, the internal cell 3A is disposed apart from the internal clock buffer cell 4A, and the wiring length of the clock wiring 5 that connects the internal clock buffer cell 4A and the internal cell 3A becomes long, and the clock skew requested by the user cannot be satisfied. In many cases, it is necessary to change the assignment of the internal cells 3 after the layout, and this places a great burden on the user. In FIG. 7, reference numeral 6 denotes a region on the chip surface where the internal cells 3 are arranged.

In view of the above, the present invention provides a method of manufacturing an integrated circuit including a design method capable of guaranteeing clock skew after layout and eliminating the burden of allocating internal cells to internal clock buffer cells. The aim is to provide a method.

[0009]

According to the present invention, there is provided a method of manufacturing an integrated circuit, comprising: an internal clock to be interposed between an input clock buffer cell for receiving a clock supplied from the outside and an internal cell requiring the clock; The logic design is performed using the internal clock buffer cells each storing the clock buffers required to drive all of the internal cells as the clock buffer cells, and an integrated circuit is manufactured.

[0010]

According to the present invention, since the internal clock buffer cell is mounted in addition to the input clock buffer cell, the clock skew after laying out the clock wiring can be guaranteed.

Further, in the present invention, an internal clock buffer cell which stores a required number of clock buffers for driving all of the internal cells requiring a clock is used as the internal clock buffer cell. Therefore, all internal cells are necessarily assigned to this internal clock buffer cell. Therefore, the burden of allocating the internal cells to the internal clock buffer cells can be eliminated.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIGS. 1 to 4, one embodiment of the present invention will be described.
An example of an integrated circuit including five internal cells will be described.

FIG. 1 is an example of a clock logic diagram. For a user, such a clock logic diagram is created, for example. In the figure, 7 is a clock input terminal, 8 is an input clock buffer cell, 9 is an internal clock buffer cell,
10 ₁ , 10 ₂ ... 10 ₁₅ are internal cells that require a clock.
“× 5” indicates that five clock buffers are required.

FIG. 2 is a connection diagram of clock wiring corresponding to the clock logic diagram of FIG. 1 created by applying the present invention, that is, a clock connection diagram. Here, the internal clock buffer cell 9 stores _five clock buffers 11 ₁ , 11 ₂ ... 115.

The clock buffers 11 ₁ , 11 ₂ ...
· 11 ₅ to connect output side, the potential of the output terminal 12 _1, 12 ₂ ... 12 ₅ of the internal clock buffer cell 9 is set to be equal.

Also, as shown in the layout diagram of FIG.
The internal clock buffer cell 9 is arranged on the chip surface at substantially the center of the area 13 where the internal cells 10 ₁ , 10 ₂ ... 10 ₁₅ are arranged, and the internal cells 10 ₁ , 10 _2.
After placing 0 ₁₅ in a predetermined position, the internal cells 10 ₁ , 10 ₂
... it is grouped 10 ₁₅ distantly to each other close five group 14 ₁ of 1 Group 3 at a time, 14 to ₂ ... 14 _5.

Then, as shown in FIG.
₁ , 14 ₅ , 14 ₂ , 14 ₄ , and 14 ₃ are connected to the output terminals 12 ₁ , 12 ₂ , 12 ₃ , 1 of the internal clock buffer cell 9 respectively.
It is assigned to 2 _4, 12 _5.

In FIG. 2, reference numeral 15 denotes a clock line connecting the input clock buffer cell 8 and the internal clock buffer cell 9, 16 ₁ , 16 ₂ , 16 ₃ , 16 ₄ , 16
₅ are output terminals 12 ₁ , 12 ₂ , 12 ₃ , 12 ₄ , 12 _{5 of} the internal clock buffer cell 9 and a group 1
4 _1, 14 _5, 14 _2, 14 _4, 14 ₃ and a clock line connecting.

4 is based on the clock connection diagram shown in FIG. 2 and shows clock wirings 15, 16 ₁ , 16 _2.
16 ₅ shows the result of layout, the present embodiment, the internal clock buffer cells and the clock lines, performs logical design as described above, is that the production of integrated circuits.

[0020] In accordance this embodiment, in addition to the input clock buffer cell 8, since the mounting the internal clock buffer cell 9, thereby laying out the clock wiring 15 _1, 16 ₂ ... 16 ₅ Later clock skew can be guaranteed.

Further, the number of clock buffer 11 ₁ needed to drive all internal cells 10 _1, 10 ₂ ... 10 ₁₅ as an internal clock buffer cell, 11 ₂ ... 11 ₅
Is used, all the internal cells 10 ₁ , 10 ₂ ... 1
0 ₁₅ is necessarily assigned to this internal clock buffer cell 9.

Therefore, it is not necessary to determine which internal cell is to be allocated to which internal clock buffer cell, and the burden of allocating the internal cell to the internal clock buffer cell as in the related art can be eliminated.

Since the internal clock buffer cell 9 is arranged substantially at the center of the region 13 where the internal cells 10 ₁ , 10 ₂ ... 10 ₁₅ are arranged, the clock wiring 16 ₁ ,
The wiring lengths of 16 ₂ ... 16 ₅ can be averaged, and clock skew can be averaged.

The internal cells 10 ₁ , 10 ₂ ... 10 ₁₅
The internal clock buffer cell 9 has a built-in clock buffer 11 ₁ ,
11 ₂ … 11 ₅ groups 14 ₁ , 14 ₂ … 1
4 ₅ , and these groups 14 ₁ , 14 _2.
· 14 ₅ one by one, since the allocation to the output terminal 12 _1, 12 ₂ ... 12 ₅ of the internal clock buffer cell 9, and averaging the load of the clock buffer 11 _1, 11 ₂ ... 11 _5, Clock skew can be averaged.

The clock buffers 11 ₁ , 11 ₂ ,.
Because, 11 ₅ and short-circuit the output side of, and the potential of the output terminal 12 _1, 12 ₂ ... 12 ₅ of the internal clock buffer cells 9 in the same, the internal cell 10 _1, 10 ₂ ... 10 ₁₅ Clocks of the same level can be supplied to achieve stable operation.

[0026]

As described above, according to the present invention, in addition to the input clock buffer cells, the internal clock buffer cells are mounted, thereby guaranteeing the clock skew after laying out the clock wiring. Can be.

Further, in the present invention, an internal clock buffer cell which stores a required number of clock buffers to drive all of the internal cells requiring a clock is used as the internal clock buffer cell. Therefore, all internal cells are necessarily assigned to this internal cell. Therefore, the burden of allocating the internal cells to the internal clock buffer cells can be eliminated.

In this case, when the internal clock buffer cells are arranged at substantially the center of the area where the internal cells requiring the clock are arranged, the wiring length of the clock wiring is averaged, and the clock skew is averaged. Can be achieved.

Also, the internal cells that require a clock are grouped into groups of the number of clock buffers stored in the internal clock buffer cells so that the internal cells that require a clock are close to each other in the same number or substantially the same number. , One by one, the internal clock buffer cells are allocated to the output terminals provided corresponding to the clock buffer, and the clock wiring is connected, the load on the clock buffer is averaged, and the clock skew is averaged. Can be.

When the output side of the clock buffer stored in the internal clock buffer cell is short-circuited, the potential of the output terminal of the internal clock buffer cell is made the same, and a clock of the same level is supplied to the internal cell requiring the clock. Supply and operation stability.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining one embodiment of the present invention;
FIG. 4 is a clock logic diagram created by a user.

FIG. 2 is a diagram for explaining one embodiment of the present invention;
FIG. 2 is a clock connection diagram corresponding to the clock logic diagram of FIG. 1 created by applying the present invention.

FIG. 3 is a diagram for explaining one embodiment of the present invention;
FIG. 3 is a diagram illustrating an arrangement position of internal clock buffer cells and grouping of internal cells.

FIG. 4 is a diagram for explaining one embodiment of the present invention;
FIG. 3 is a layout diagram created based on the clock connection diagram of FIG. 2.

FIG. 5 is a clock logic diagram showing an example of a conventional integrated circuit.

FIG. 6 is a clock logic diagram showing another example of a conventional integrated circuit.

FIG. 7 is a layout diagram for explaining a problem of the conventional integrated circuit shown in FIG. 6;

[Explanation of symbols]

7 clock input terminal 8 input clock buffer cell 9 internal clock buffer cell 10 ₁ , 10 ₂ , internal cell requiring 10 ₁₅ clocks

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 27/04 H01L 21/82 H01L 21/822

Claims (3)

(57) [Claims] An internal clock buffer cell to be interposed between an input clock buffer cell for taking in a clock supplied from the outside and a plurality of internal cells requiring the clock, all of the plurality of internal cells are used as internal clock buffer cells. storing a plurality of clock buffers number of required to drive,
In addition, the output sides of the plurality of clock buffers are all short-circuited.
A logic design using the internal clock buffer cell described above to manufacture an integrated circuit. 2. The method according to claim 2, wherein the plurality of internal clock buffer cells are
2. The method of manufacturing an integrated circuit according to claim 1, wherein the semiconductor device is arranged at a substantially central portion of a region where the internal cell is formed. 3. The logic design includes internal cells that are close in distance.
Are grouped together, and the internal cells of each group
The plurality of internal cells are grouped into groups of the number of clock buffers stored in the internal clock buffer cells so that the number of the internal cells is equal to or substantially equal to each other. 3. The integrated circuit according to claim 1 , further comprising a step of connecting a clock wiring by assigning the clock buffer cell to an output terminal provided corresponding to the clock buffer. Method.