JPS60254762A - Package for semiconductor element - Google Patents

Package for semiconductor element

Info

Publication number
JPS60254762A
JPS60254762A JP59111264A JP11126484A JPS60254762A JP S60254762 A JPS60254762 A JP S60254762A JP 59111264 A JP59111264 A JP 59111264A JP 11126484 A JP11126484 A JP 11126484A JP S60254762 A JPS60254762 A JP S60254762A
Authority
JP
Japan
Prior art keywords
packages
contact pieces
terminals
semiconductor elements
formed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59111264A
Inventor
Shohei Ikehara
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP59111264A priority Critical patent/JPS60254762A/en
Publication of JPS60254762A publication Critical patent/JPS60254762A/en
Application status is Granted legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes
    • H01L25/10Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/113Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134Stud bumping, i.e. using a wire-bonding apparatus
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16135Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16147Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a bonding area disposed in a recess of the surface
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047Details of electrical connections between containers
    • H01L2225/1058Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00013Fully indexed content
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA

Abstract

PURPOSE:To set address data for selecting semiconductor elements and to facilitate the increase and decrease in number of the semiconductor elements to be mounted, by providing contact pieces on the upper surfaces of packages, and mounting a plurality of the packages. CONSTITUTION:Terminals 6 are provided at one side of a member 9 made of a ceramic material and the like. Contact pieces 7 are provided on the other side. Tip parts 6A are formed so that they can be inserted and pulled out. The terminals 6 and the contact pieces 7 are connected to semiconductor elements to be mounted through pattern wirings 8A, 8B and 8C. The increase and decrease in memory capacity are carried out by changing the number of mounting stages of packages 5. For the packages 5-1-5-4, inverters I are formed between the terminals 6-1 and the contact pieces 7-1, and exclusive OR gates G are formed between the terminals 6-2 and the contact pieces 7-2. Therefore, address data can be set based on the mounting sequence of the packages.
JP59111264A 1984-05-31 1984-05-31 Package for semiconductor element Granted JPS60254762A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59111264A JPS60254762A (en) 1984-05-31 1984-05-31 Package for semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59111264A JPS60254762A (en) 1984-05-31 1984-05-31 Package for semiconductor element

Publications (1)

Publication Number Publication Date
JPS60254762A true JPS60254762A (en) 1985-12-16

Family

ID=14556788

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59111264A Granted JPS60254762A (en) 1984-05-31 1984-05-31 Package for semiconductor element

Country Status (1)

Country Link
JP (1) JPS60254762A (en)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4953005A (en) * 1987-04-17 1990-08-28 Xoc Devices, Inc. Packaging system for stacking integrated circuits
WO1991000619A1 (en) * 1989-06-30 1991-01-10 Raychem Corporation Flying leads for integrated circuits
US5028986A (en) * 1987-12-28 1991-07-02 Hitachi, Ltd. Semiconductor device and semiconductor module with a plurality of stacked semiconductor devices
US5198888A (en) * 1987-12-28 1993-03-30 Hitachi, Ltd. Semiconductor stacked device
JPH07130949A (en) * 1993-11-01 1995-05-19 Nec Corp Semiconductor device
US5514907A (en) * 1995-03-21 1996-05-07 Simple Technology Incorporated Apparatus for stacking semiconductor chips
US5648683A (en) * 1993-08-13 1997-07-15 Kabushiki Kaisha Toshiba Semiconductor device in which a first resin-encapsulated package is mounted on a second resin-encapsulated package
US6340845B1 (en) 1999-01-22 2002-01-22 Nec Corporation Memory package implementing two-fold memory capacity and two different memory functions
US6576992B1 (en) 2001-10-26 2003-06-10 Staktek Group L.P. Chip scale stacking system and method
US6806120B2 (en) 2001-03-27 2004-10-19 Staktek Group, L.P. Contact member stacking system and method
KR101078744B1 (en) 2010-05-06 2011-11-02 주식회사 하이닉스반도체 Stacked semiconductor package

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4953005A (en) * 1987-04-17 1990-08-28 Xoc Devices, Inc. Packaging system for stacking integrated circuits
US5028986A (en) * 1987-12-28 1991-07-02 Hitachi, Ltd. Semiconductor device and semiconductor module with a plurality of stacked semiconductor devices
US5198888A (en) * 1987-12-28 1993-03-30 Hitachi, Ltd. Semiconductor stacked device
WO1991000619A1 (en) * 1989-06-30 1991-01-10 Raychem Corporation Flying leads for integrated circuits
US5648683A (en) * 1993-08-13 1997-07-15 Kabushiki Kaisha Toshiba Semiconductor device in which a first resin-encapsulated package is mounted on a second resin-encapsulated package
JPH07130949A (en) * 1993-11-01 1995-05-19 Nec Corp Semiconductor device
US5514907A (en) * 1995-03-21 1996-05-07 Simple Technology Incorporated Apparatus for stacking semiconductor chips
USRE36916E (en) * 1995-03-21 2000-10-17 Simple Technology Incorporated Apparatus for stacking semiconductor chips
US6340845B1 (en) 1999-01-22 2002-01-22 Nec Corporation Memory package implementing two-fold memory capacity and two different memory functions
US6806120B2 (en) 2001-03-27 2004-10-19 Staktek Group, L.P. Contact member stacking system and method
US6576992B1 (en) 2001-10-26 2003-06-10 Staktek Group L.P. Chip scale stacking system and method
KR101078744B1 (en) 2010-05-06 2011-11-02 주식회사 하이닉스반도체 Stacked semiconductor package

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