JPH05190674A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPH05190674A JPH05190674A JP2179292A JP2179292A JPH05190674A JP H05190674 A JPH05190674 A JP H05190674A JP 2179292 A JP2179292 A JP 2179292A JP 2179292 A JP2179292 A JP 2179292A JP H05190674 A JPH05190674 A JP H05190674A
- Authority
- JP
- Japan
- Prior art keywords
- pads
- chip
- integrated circuit
- semiconductor integrated
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、半導体集積回路装置に
関し、特にチップ上の外部引き出し用電極(以下、パッ
ドという)の配置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to the arrangement of external extraction electrodes (hereinafter referred to as pads) on a chip.
【0002】[0002]
【従来の技術】図3の(a)は、従来の半導体集積回路
装置のパッケージ上への実装状態を示す平面図である。
同図において、1は半導体集積回路装置のチップ、2は
チップ1上に配置されたパッド、4はパッケージ、5は
リードである。2. Description of the Related Art FIG. 3A is a plan view showing a mounting state of a conventional semiconductor integrated circuit device on a package.
In the figure, 1 is a chip of a semiconductor integrated circuit device, 2 is a pad arranged on the chip 1, 4 is a package, and 5 is a lead.
【0003】同図に示されるように、2辺からリードが
導出されているパッケージに、チップの2辺にパッドが
配列されている半導体集積回路装置を実装する場合、リ
ードとのボンディングの容易性を考慮して、チップは、
チップ上のパッドがパッケージのリードと対向する位置
にくるように配置される。As shown in FIG. 1, when a semiconductor integrated circuit device having pads arranged on two sides of a chip is mounted on a package in which leads are led out from two sides, it is easy to bond the leads. Taking into account
The pads on the chip are arranged so as to face the leads of the package.
【0004】[0004]
【発明が解決しようとする課題】上述した従来の半導体
集積回路装置では、パッドが特定のパッケージに実装し
やすい配置になされているため、図3の(b)に示すよ
うなこのパッケージとは異なる側にリードが導出されて
いるパッケージ上には実装することは困難であった。そ
のため、リード導出方向の異なるパッケージにこの半導
体集積回路装置を実装する必要が生じた場合には、パッ
ドの配置を隣接した辺側に移したチップを設計し直さな
ければならないことになり、設計、製造のコストを増大
させる原因となっていた。In the above-described conventional semiconductor integrated circuit device, the pads are arranged so as to be easily mounted in a specific package, and therefore, this package is different from this package as shown in FIG. 3B. It was difficult to mount on a package in which the leads are led out to the side. Therefore, when it becomes necessary to mount this semiconductor integrated circuit device in a package having different lead derivation directions, it is necessary to redesign the chip in which the pad arrangement is moved to the adjacent side. This has been a cause of increasing the manufacturing cost.
【0005】[0005]
【課題を解決するための手段】本発明の半導体集積回路
装置は、半導体基板の対向する2辺に外部引き出し用の
第1群のパッドが配置され、前記対向する2辺に隣接し
た2辺に前記第1群のパッドとそれぞれ対をなす第2群
のパッドが配置され、第1群のパッドと第2群のパッド
とは対をなすパッド同士で電気的に接続されているもの
である。In a semiconductor integrated circuit device according to the present invention, a first group of pads for external extraction are arranged on two opposite sides of a semiconductor substrate, and the two sides adjacent to the opposite two sides are arranged. A second group of pads, each pairing with the first group of pads, is arranged, and the first group of pads and the second group of pads are electrically connected to each other.
【0006】[0006]
【実施例】次に、本発明の実施例について図面を参照し
て説明する。図1の(a)は、本発明の第1の実施例の
平面図である。同図において、1は半導体集積回路装置
のチップ、2は内部の素子と接続された外部引き出し用
のパッド、3はパッド間接続用配線である。Embodiments of the present invention will now be described with reference to the drawings. FIG. 1A is a plan view of the first embodiment of the present invention. In the figure, 1 is a chip of a semiconductor integrated circuit device, 2 is a pad for external extraction connected to an internal element, and 3 is a wiring for connecting pads.
【0007】図1の(a)に示されるように、本発明で
は、チップの上下辺と左右辺とに、それぞれ同数の同一
機能のパッドを配置し、同一機能のパッド同士を配線3
によって接続したものである。As shown in FIG. 1A, in the present invention, the same number of pads having the same function are arranged on the upper and lower sides and the left and right sides of the chip, and the pads having the same function are connected to each other by wiring 3.
Are connected by.
【0008】図1の(a)に示された半導体集積回路装
置は、図2の(a)または(b)に示すようにパッケー
ジ内に実装される。パッケージ4が、図2の(a)に示
すように、リード5が左右に配置されたものである場合
には、チップ1上の左右に配置されたパッド2がリード
5と接続され、図2の(b)に示すリード5が上下に導
出されたパッケージを用いる場合には、チップ1上の上
下に配置されたパッド2が用いられる。The semiconductor integrated circuit device shown in FIG. 1 (a) is mounted in a package as shown in FIG. 2 (a) or (b). When the package 4 has the leads 5 arranged on the left and right as shown in FIG. 2A, the pads 2 arranged on the left and right on the chip 1 are connected to the leads 5, and In the case of using a package in which the leads 5 shown in (b) are led out vertically, the pads 2 placed above and below the chip 1 are used.
【0009】従って、本実施例の半導体集積回路装置で
は、これを実装するためのパッケージの型が変更されて
もチップはそのまま実装できるため、新たに半導体集積
回路装置を設計し製造する手間を省くことができる。Therefore, in the semiconductor integrated circuit device of this embodiment, the chip can be mounted as it is even if the type of the package for mounting the same is changed, so that the labor for newly designing and manufacturing the semiconductor integrated circuit device is saved. be able to.
【0010】図1の(b)乃至(d)は、本発明の第2
乃至第4の実施例を示す平面図である。図1の(a)の
実施例では、パッケージのリードの配列を図2の(a)
と(b)で変えなくてははらなかったが、図1の(b)
の実施例の場合には、パッケージのリード配列を変えな
くてもすむという利点がある。図1の(c)の実施例で
は、パッド間接続配線を交差させなくて済み、また、こ
の配線の長さも短かくすることができる。1 (b) to 1 (d) show a second embodiment of the present invention.
It is a top view showing a 4th example. In the embodiment shown in FIG. 1A, the package lead arrangement is shown in FIG.
I had to change between (b) and
In the case of the above embodiment, there is an advantage that the lead arrangement of the package does not have to be changed. In the embodiment of FIG. 1C, it is not necessary to intersect the inter-pad connection wiring, and the length of this wiring can be shortened.
【0011】[0011]
【発明の効果】以上説明したように、本発明の半導体集
積回路装置は、チップ上のパッドを上下辺に配置される
ものと左右辺に配置されるものとの2群に分け、それぞ
れの群の同じ入出力信号を受ける機能を持つパッド同士
を配線で接続したものであるので、本発明によれば、半
導体集積回路装置を実装するためのパッケージのリード
導出方向が変更されても同一のチップをそのまま実装す
ることが可能となる。従って、本発明によれば、実装用
パッケージの型が変更されても半導体集積回路装置を新
たに設計し製造し直す必要がなくなるので、資源の有効
利用が可能となりコストダウンを図ることができる。As described above, in the semiconductor integrated circuit device of the present invention, the pads on the chip are divided into two groups, one arranged on the upper and lower sides and one arranged on the left and right sides, and each group. According to the present invention, since the pads having the function of receiving the same input / output signal are connected by wiring, the same chip can be used even if the lead lead-out direction of the package for mounting the semiconductor integrated circuit device is changed. Can be implemented as is. Therefore, according to the present invention, it is not necessary to newly design and remanufacture the semiconductor integrated circuit device even if the type of the mounting package is changed, so that the resources can be effectively used and the cost can be reduced.
【図1】本発明の第1乃至第4の実施例の平面図。FIG. 1 is a plan view of first to fourth embodiments of the present invention.
【図2】本発明の実施例の実装状態を示す平面図。FIG. 2 is a plan view showing a mounted state of the embodiment of the invention.
【図3】従来例の実装状態を示す平面図。FIG. 3 is a plan view showing a mounting state of a conventional example.
1 半導体集積回路装置のチップ 2 パッド 3 パッド間接続用配線 4 パッケージ 5 リード 1 Chip of semiconductor integrated circuit device 2 Pad 3 Wiring for pad connection 4 Package 5 Lead
Claims (1)
し用の第1群のパッドが配置され、前記対向する2辺に
隣接した2辺に前記第1群のパッドとそれぞれ対をなす
第2群のパッドが配置され、第1群のパッドと第2群の
パッドとは対をなすパッド同士で電気的に接続されてい
る半導体集積回路装置。1. A first group of pads for external extraction are arranged on two opposite sides of a semiconductor substrate, and a second pair of pads for the first group is formed on two sides adjacent to the opposite two sides. A semiconductor integrated circuit device in which pads of a group are arranged, and pads of the first group and pads of the second group are electrically connected to each other by a pair of pads.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2179292A JPH05190674A (en) | 1992-01-10 | 1992-01-10 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2179292A JPH05190674A (en) | 1992-01-10 | 1992-01-10 | Semiconductor integrated circuit device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH05190674A true JPH05190674A (en) | 1993-07-30 |
Family
ID=12064912
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2179292A Pending JPH05190674A (en) | 1992-01-10 | 1992-01-10 | Semiconductor integrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH05190674A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006286688A (en) * | 2005-03-31 | 2006-10-19 | Elpida Memory Inc | Semiconductor device |
US8637998B2 (en) | 2010-11-25 | 2014-01-28 | Renesas Electronics Corporation | Semiconductor chip and semiconductor device |
-
1992
- 1992-01-10 JP JP2179292A patent/JPH05190674A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006286688A (en) * | 2005-03-31 | 2006-10-19 | Elpida Memory Inc | Semiconductor device |
US8637998B2 (en) | 2010-11-25 | 2014-01-28 | Renesas Electronics Corporation | Semiconductor chip and semiconductor device |
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