JPH01289276A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH01289276A
JPH01289276A JP63120908A JP12090888A JPH01289276A JP H01289276 A JPH01289276 A JP H01289276A JP 63120908 A JP63120908 A JP 63120908A JP 12090888 A JP12090888 A JP 12090888A JP H01289276 A JPH01289276 A JP H01289276A
Authority
JP
Japan
Prior art keywords
semiconductor chip
semiconductor device
lead frame
signal lines
power
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63120908A
Other languages
Japanese (ja)
Inventor
Yoshinaga Inoue
井上　好永
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP63120908A priority Critical patent/JPH01289276A/en
Publication of JPH01289276A publication Critical patent/JPH01289276A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To make a semiconductor chip small-sized and to reduce an influence by a noise or the like with reference to other signal lines by a method wherein one power supply or signal is connected by using two or more conductors from both sides of the semiconductor chip. CONSTITUTION:One or more lead frames 1 are arranged at the upper side or the lower side of a die pad 3 where a semiconductor chip 2 is mounted and two or more conductors 4 are connected to both sides of the semiconductor chip 2 from the lead frames 1. Accordingly, it is not required that power-supply lines 5 or signal lines on the semiconductor chip 2 are wired from one end to the other end of the semiconductor chip 2. By this setup, the semiconductor chip 2 can be made small-sized and it is possible to reduce an influence by a noise or the like with reference to other signal lines.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、半導体集積装置のフレーム構造、及びフレ
ームとチップをつなぐ４線を接続する組立技術に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a frame structure of a semiconductor integrated device and an assembly technique for connecting four wires connecting the frame and a chip.

〔従来の技術〕[Conventional technology]

第３図は従来の半導体装ｌｔを示す上面図であシ、図に
おいて、（１）はリード・フレーム、（２）は半導体チ
ップ、（３）は半導体チップ（２）を載せるダイパッド
、（４）はリード・フレーム（１）と半導体チップ（２
）との間に接続され電源を伝える辱Ｍ、（５）は半導体
チップ（２）上に配置された電源線である。１つのリー
ド・フレーム（１）に対して、１本の導線（４）により
半導体チップ（２）に接続され半導体チップ（２）上の
電源環（５）に電源が伝えられる。FIG. 3 is a top view showing a conventional semiconductor device lt. In the figure, (1) is a lead frame, (2) is a semiconductor chip, (3) is a die pad on which the semiconductor chip (2) is placed, and (4) is a top view of a conventional semiconductor device. ) is a lead frame (1) and a semiconductor chip (2).
) and transmitting power, (5) is a power line arranged on the semiconductor chip (2). One lead frame (1) is connected to a semiconductor chip (2) by one conductor wire (4), and power is transmitted to a power ring (5) on the semiconductor chip (2).

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来の半導体装置は、以上のように構成されているため
、１つの電源線や信号線が半導体チップ上において、端
から端へと引き回さなければならず、半導体チップの大
きさが大きくなったシ、いろいろな回路を配置できなく
なるばかりでなく、また、他の信号線から生ずるノイズ
等の影響を受けたシ、他の信号線に影響を及ぼしやすい
などの問題点があった。Conventional semiconductor devices are configured as described above, so a single power supply line or signal line must be routed from end to end on the semiconductor chip, which increases the size of the semiconductor chip. However, it not only makes it impossible to arrange various circuits, but also causes problems such as being affected by noise generated from other signal lines and easily affecting other signal lines.

この発明は上記のような問題点を解消するためにな嘔れ
たもので、半導体チップ上において、電源線又は信Ｊｊ
＋線を引き回さなくても良く、半導体チップの大きさを
小さくしたυ、いろいろな回路を配置したシ、また、他
の信号線とのノイズ等の影響が少ない電気特性の艮い半
導体装ｍを得ることを目的とする。This invention was developed to solve the above-mentioned problems.
Semiconductor devices that eliminate the need to run + wires, reduce the size of the semiconductor chip, have various circuits arranged, and have excellent electrical characteristics that are less affected by noise from other signal lines. The purpose is to obtain m.

〔課題を解決するための手段〕[Means to solve the problem]

この発明に係る半導体装置は、半導体チップを載せるダ
イ・パッドの下側又は上側に、１つ又はそれ以上のり−
ド・フレームを配置し、そのリード・フレームより半導
体チップへと２本又はそれ以上の導線により接続したも
のである。A semiconductor device according to the present invention has one or more adhesive layers on the lower side or upper side of a die pad on which a semiconductor chip is mounted.
The lead frame is connected to the semiconductor chip by two or more conductive wires.

〔作用〕[Effect]

この発明における半導体装置は、ある１つの電源又は信
号を半導体チップの両サイドから２本又はそれ以上の導
線を用いて接続することにより、半導体チップ上で端か
ら端へと電源線又は信号線を引き回しｆｃ副配線しなく
て済む。The semiconductor device of the present invention connects one power supply or signal from both sides of the semiconductor chip using two or more conductive wires, thereby connecting the power supply line or signal line from one end to the other on the semiconductor chip. There is no need to route fc sub-wiring.

〔実施例〕〔Example〕

以下、この発明の一実施例を図について説明する。第１
図は半導体装置の上面図、第２図は第１図のｘ−ｘにお
ける断面図である。図において、（１）〜（５）は第３
図の従来例に示したものと同等であるので説明を省略す
る。リード・フレーム（１）はダイ・パッド（３）の下
側、すなわち、半導体チップ（２）が載っている面の反
対側にダイパッド（３）と接触しないように配置されて
いる。リード＠フレーム（１）からは２本の導線（４）
により、半導体チップの両サイドへ接続されている。An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a top view of the semiconductor device, and FIG. 2 is a sectional view taken along line xx in FIG. 1. In the figure, (1) to (5) are the third
Since this is the same as that shown in the conventional example in the figure, the explanation will be omitted. The lead frame (1) is placed below the die pad (3), that is, on the opposite side of the surface on which the semiconductor chip (2) is mounted, so as not to come into contact with the die pad (3). Lead @ Two conductors (4) from the frame (1)
are connected to both sides of the semiconductor chip.

以上により、半導体チップ（２）上に配置された電源線
（５）は第１図に示すごとく、従来例に比べて２分割と
なっている。As a result of the above, the power supply line (5) arranged on the semiconductor chip (2) is divided into two parts, as shown in FIG. 1, compared to the conventional example.

なお、上記の実施例では、リード・フレーム（１）の内
１つがダイ鎗パッド（３）の下側に配置されていたが、
上側でも良く、リード・フレーム（１）は２つでも、そ
れ以上でも良い。In addition, in the above embodiment, one of the lead frames (1) was placed below the die ring pad (3), but
It may be on the upper side, and there may be two or more lead frames (1).

また、１つのリード・フレーム（１）よ９２本の導線（
４）が半導体チップ（２）に接続されていたが、３本で
も、それ以上でも良い。Also, one lead frame (1) has 92 conductors (
4) is connected to the semiconductor chip (2), but there may be three or more.

また、電源線（５）であったが、信号線でも良い。Further, although the power line (5) is used, it may be a signal line.

〔弁明の効果〕[Effect of excuse]

以上のように、この発明によれば、ダイパッドの下側、
又は上側にリード・フレームを配置し、半導体チップの
両サイドから電源線又は信号線を接続するように構成し
たので、半導体チップ上の電源線又はＭ導線を半導体チ
ップ上を端からＩｖｉまで配線しなくても済むため、半
導体チップを小さくできたシ、他の回路ｆ：配装したシ
、また、他の信号線とのノイズ等の影響を及ぼし合いに
くくなり、電気特性上、良質なものが得られる効果があ
る０As described above, according to the present invention, the lower side of the die pad,
Alternatively, a lead frame is placed on the upper side and the power line or signal line is connected from both sides of the semiconductor chip, so the power line or M conductor on the semiconductor chip can be routed from the edge to Ivi on the semiconductor chip. This allows the semiconductor chip to be made smaller, other circuits and other circuits to be arranged, and noise from other signal lines to be less likely to affect each other. There is an effect that can be obtained 0

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はこの発明の一実施例による半導体装置の上面図
、第２図は第１図のｘ＠ｘにおける断面図、第３図は従
来の半導体装置を示す上面図である０ 図において、（１）はリード・フレーム、（２）は半導
体チップ、（３）はダイ・パッド、（４）は導線、（５
）は電源線である。 なお、図中同一符号は同−又は相当部分を示す。FIG. 1 is a top view of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a sectional view at x@x in FIG. 1, and FIG. 3 is a top view of a conventional semiconductor device. (1) is the lead frame, (2) is the semiconductor chip, (3) is the die pad, (4) is the conductor, (5) is the
) is the power line. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims] 　半導体集積回路チップを載せるダイ・パッドの下側又
は上側に、１つ又はそれ以上の外部信号及び電源を伝え
るリード・フレームを配置し、そのリード・フレームか
ら、２本又はそれ以上の導線により接続したことを特徴
とする半導体装置。A lead frame for transmitting one or more external signals and power is placed below or above a die pad on which a semiconductor integrated circuit chip is mounted, and the leads are connected by two or more conductive wires from the lead frame. A semiconductor device characterized by:
JP63120908A 1988-05-17 1988-05-17 Semiconductor device Pending JPH01289276A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63120908A JPH01289276A (en) 1988-05-17 1988-05-17 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63120908A JPH01289276A (en) 1988-05-17 1988-05-17 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH01289276A true JPH01289276A (en) 1989-11-21

Family

ID=14797976

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63120908A Pending JPH01289276A (en) 1988-05-17 1988-05-17 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH01289276A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5715147A (en) * 1990-12-20 1998-02-03 Kabushiki Kaisha Toshiba Semiconductor device having an interconnecting circuit board
US6608368B2 (en) * 1997-02-27 2003-08-19 Seiko Epson Corporation Semiconductor device with power source conductor pattern and grounding conductor pattern

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5715147A (en) * 1990-12-20 1998-02-03 Kabushiki Kaisha Toshiba Semiconductor device having an interconnecting circuit board
US6608368B2 (en) * 1997-02-27 2003-08-19 Seiko Epson Corporation Semiconductor device with power source conductor pattern and grounding conductor pattern

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