JPH09293822A - Semiconductor device with lead frame for power source only - Google Patents

Semiconductor device with lead frame for power source only

Info

Publication number
JPH09293822A
JPH09293822A JP10531296A JP10531296A JPH09293822A JP H09293822 A JPH09293822 A JP H09293822A JP 10531296 A JP10531296 A JP 10531296A JP 10531296 A JP10531296 A JP 10531296A JP H09293822 A JPH09293822 A JP H09293822A
Authority
JP
Japan
Prior art keywords
lead frame
semiconductor device
power source
semiconductor
dedicated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10531296A
Other languages
Japanese (ja)
Inventor
Hiroyuki Yano
博之 矢野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP10531296A priority Critical patent/JPH09293822A/en
Publication of JPH09293822A publication Critical patent/JPH09293822A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48237—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To reduce the number of power source pins, increase the number of semiconductor signal pins, and reduce the size and cost of a semiconductor package. SOLUTION: A metal lead frame for use in assembling of a semiconductor device has a lead frame 101 for VDD power source only and a semiconductor supporting lead frame 102 also used for a VSS power source. A semiconductor device 103 is adhered to an insulation adhesive to the latter lead frame 102. The former lead frame 101 is located vertically above an electric signal transmitting lead frame 108 and formed as a ring surrounding the periphery of the semiconductor device 103. Owing to this structure, any semiconductor pad can be connected through a binding wire to the power-only lead frame.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体装置の組立
に使用するリードフレームに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame used for assembling a semiconductor device.

【０００２】[0002]

【従来の技術】従来の半導体装置の組立に使用するリー
ドフレームを、図２により説明する。図２は、従来の一
実施例の半導体装置を示しており、２０１はＶＤＤ電源
リードフレーム、２０２はＶＳＳ電源リードフレームで
あり、この例では電源用として使っている。２０４は半
導体装置、２０３は半導体装置支持用リードフレーム、
２０５はボンディングワイヤー、２０６はＶＤＤ電源パ
ッド、２０７はＶＳＳ電源パッドであり、半導体装置２
０４は半導体支持用リードフレームに接着し固定してあ
る。また、ＶＤＤ電源リードフレーム２０１はボンディ
ングワイヤー２０５によってＶＤＤ電源パッド２０６に
電気的に接続している。これにより、半導体装置２０４
にＶＤＤ電源を供給している。同様にＶＳＳ電源リード
フレーム２０２はボンディングワイヤー２０５によっ
て、ＶＳＳ電源パッド２０７に電気的に接続される。こ
れによりＶＳＳ電源を半導体装置２０４に供給してい
る。２０９は電気信号伝達用リードフレーム、２０８は
信号パッドであり、電気信号伝達用リードフレーム２０
９はボンデイングワイヤー２０５によって信号パッド２
０８に電気的に接続されている。これにより、電気信号
を半導体装置２０４に入力あるいは出力する事が出来
る。2. Description of the Related Art A lead frame used for assembling a conventional semiconductor device will be described with reference to FIG. FIG. 2 shows a semiconductor device of a conventional example, 201 is a VDD power supply lead frame, and 202 is a VSS power supply lead frame, which is used for power supply in this example. Reference numeral 204 is a semiconductor device, 203 is a lead frame for supporting the semiconductor device,
Reference numeral 205 is a bonding wire, 206 is a VDD power supply pad, and 207 is a VSS power supply pad.
Reference numeral 04 is adhered and fixed to the semiconductor supporting lead frame. Further, the VDD power supply lead frame 201 is electrically connected to the VDD power supply pad 206 by a bonding wire 205. As a result, the semiconductor device 204
VDD power is supplied to. Similarly, the VSS power supply lead frame 202 is electrically connected to the VSS power supply pad 207 by a bonding wire 205. This supplies the VSS power to the semiconductor device 204. Reference numeral 209 is an electric signal transmission lead frame, and 208 is a signal pad.
9 is a signal pad 2 by a bonding wire 205
08 is electrically connected. Accordingly, an electric signal can be input to or output from the semiconductor device 204.

【０００３】[0003]

【発明が解決しようとする課題】上記の従来の半導体装
置の組立に使用するリードフレームは、一つの電源パッ
ドに対して一つのリードフレームを必要としていたた
め、電源ピンが電源パッド分だけ必要となり、ピン数の
増加、半導体パッケージの大型化、組立コストの増加を
まねくという課題を有する。The lead frame used for assembling the above-mentioned conventional semiconductor device requires one lead frame for one power supply pad, so that power supply pins are required for each power supply pad. The problem is that the number of pins increases, the size of the semiconductor package increases, and the assembly cost increases.

【０００４】また、半導体装置を安定して動作させるた
めにはどうしても複数電源ピンを設ける必要が生じ、電
源ピン数を減らすことが難しかった。Further, in order to operate the semiconductor device stably, it is necessary to provide a plurality of power supply pins, and it is difficult to reduce the number of power supply pins.

【０００５】そこで、本発明はこのような課題を解決す
るもので、その目的とするところは、電源ピン数を増加
させる事なく、半導体装置を安定動作させるところにあ
る。Therefore, the present invention solves such a problem, and an object thereof is to stably operate a semiconductor device without increasing the number of power supply pins.

【０００６】[0006]

【課題を解決するための手段】本発明の電源専用リード
フレーム付半導体装置は、半導体装置の組立に使用する
金属製リードフレームにおいて、半導体装置を支える電
源兼用半導体支持リードフレームと電気信号を伝達する
ためのリードフレームと電源専用リードフレームとから
なり、半導体装置を支えるリードフレームと半導体装置
とを電気的に接続するボンディングワイヤーによって接
続され、電気信号を伝達するためのリードフレームはボ
ンディングワイヤーによって半導体装置のパッド部分と
電気的に接続され、さらに電源専用リードフレームは、
電気信号を伝達するためのリードフレームの垂直上方向
に位置し、半導体装置の周辺を囲むように輪を形成した
リードフレームを配置したことを特徴とする。In a semiconductor device with a lead frame for exclusive use of a power source of the present invention, in a metal lead frame used for assembling a semiconductor device, an electric signal is transmitted to a semiconductor supporting lead frame also serving as a power source for supporting the semiconductor device. A lead frame for power supply and a lead frame for exclusive use of a power source. The lead frame for supporting the semiconductor device is connected by a bonding wire for electrically connecting the semiconductor device, and the lead frame for transmitting an electric signal is the semiconductor device by the bonding wire. It is electrically connected to the pad part of the
It is characterized in that a lead frame is arranged vertically above the lead frame for transmitting an electric signal and has a ring formed so as to surround the periphery of the semiconductor device.

【０００７】[0007]

【発明の実施の形態】以下、本発明の一実施例を図面に
より説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings.

【０００８】図１は，本発明の一実施例における電源専
用リードフレーム付半導体装置を示しており、１０１は
ＶＤＤ電源専用リードフレーム、１０８は電気信号伝達
用リードフレーム、１０２はＶＳＳ電源兼用半導体支持
リードフレーム、１０３は半導体装置であり、半導体装
置１０３はＶＳＳ電源兼用半導体支持リードフレーム１
０２の上に絶縁性の接着剤によつて絶縁するように張り
付けてある。また、ＶＤＤ電源専用リードフレーム１０
１は、電気信号伝達用リードフレーム１０８の垂直上方
向に位置し、半導体装置１０３の周辺を囲むように輪を
形成して配置されている。さらに図１に示したＶＤＤ電
源専用リードフレーム１０１の右上、左下へのびる部分
はＶＤＤ電源ピンとして半導体パッケージの外に出さ
れ、なおかつ、ＶＤＤ電源専用リードフレーム１０１を
支える役割を果たす。１０７はＶＤＤ電源パッド、１０
４はボンディングワイヤーであり、ＶＤＤ電源パッド１
０７はボンディングワイヤー１０４によってＶＤＤ電源
専用リードフレーム１０１に電気的に接続される。これ
により半導体装置１０３にＶＤＤ電源が供給される。１
０６はＶＳＳ電源パッド、１０５はボンディングワイヤ
ーであり、ＶＳＳ電源パッド１０６はボンディングワイ
ヤー１０５によって、ＶＳＳ電源兼用半導体支持リード
フレーム１０２に電気的に接続される。これにより、半
導体装置１０３にＶＳＳ電源が供給される。半導体装置
１０３はＶＳＳ電源パッド１０６及び、ＶＤＤ電源パッ
ド１０７が多くあればあるほど安定動作し有利になる。
前述した構造にしたためＶＤＤ電源専用リードフレーム
１０１およびＶＳＳ電源兼用半導体支持リードフレーム
１０２に対して複数ボンディングでき、なおかつ他のボ
ンディングワイヤーと接触しないように接続することが
出来る。FIG. 1 shows a semiconductor device with a lead frame dedicated to a power source according to an embodiment of the present invention. 101 is a lead frame dedicated to a VDD power source, 108 is a lead frame for transmitting an electric signal, and 102 is a semiconductor support also serving as a VSS power source. A lead frame 103 is a semiconductor device, and the semiconductor device 103 is a semiconductor supporting lead frame 1 that also serves as a VSS power source.
No. 02 is attached by an insulating adhesive so as to be insulated. In addition, the lead frame 10 dedicated to the VDD power source
1 is positioned vertically above the electric signal transmission lead frame 108, and is arranged so as to form a ring so as to surround the periphery of the semiconductor device 103. Further, the upper right portion and the lower left portion of the lead frame 101 dedicated to the VDD power source shown in FIG. 1 are exposed to the outside of the semiconductor package as the VDD power source pin, and also serve to support the lead frame 101 dedicated to the VDD power source. 107 is a VDD power supply pad, 10
4 is a bonding wire, VDD power supply pad 1
Reference numeral 07 is electrically connected to the lead frame 101 dedicated to the VDD power source by the bonding wire 104. As a result, the VDD power is supplied to the semiconductor device 103. 1
Reference numeral 06 is a VSS power supply pad, 105 is a bonding wire, and the VSS power supply pad 106 is electrically connected to the VSS supporting semiconductor supporting lead frame 102 by the bonding wire 105. As a result, the VSS power is supplied to the semiconductor device 103. The semiconductor device 103 is more stable and more advantageous as the number of VSS power supply pads 106 and VDD power supply pads 107 increases.
Because of the above-described structure, it is possible to perform a plurality of bondings to the lead frame 101 dedicated to the VDD power source and the semiconductor supporting lead frame 102 also serving as the VSS power source, and also to connect without contacting other bonding wires.

【０００９】また、１０９は電気信号入力パッドであ
り、電気信号入力パッド１０９を電気信号伝達用リード
フレームではなく、ＶＤＤ電源専用リードフレーム１０
１およびＶＳＳ電源兼用半導体支持リードフレーム１０
２へボンディングワイヤー１１０を使って接続すること
により、半導体装置の一部分のみを活性化させたり、半
導体装置の機能を変更するのに使用することができる。Further, 109 is an electric signal input pad, and the electric signal input pad 109 is not the lead frame for electric signal transmission but the lead frame 10 dedicated to the VDD power source.
1 and VSS supporting power semiconductor supporting lead frame 10
The bonding wire 110 can be used for activating only a part of the semiconductor device or changing the function of the semiconductor device.

【００１０】なお、本実施例ではＶＤＤ電源専用リード
フレーム１０１の形状が半導体装置の周辺を囲むように
輪を形成しているが、半導体装置の１辺以上ととなり合
うような棒状としたＶＤＤ電源専用リードフレームで
も、同様の効果を得ることが出来る。In this embodiment, the lead frame 101 dedicated to the VDD power supply is formed in a ring shape so as to surround the periphery of the semiconductor device. The same effect can be obtained with a dedicated lead frame.

【００１１】[0011]

【発明の効果】以上述べたように、本発明によれば半導
体装置の周囲に電源専用リードフレームを備えたことに
より、どのパッドからでもボンディングワイヤーによっ
て電源のリードフレームに接続することができ、電源ピ
ンが一対であっても複数の電源パッドに接続することが
出来る。これにより半導体装置の安定動作に寄与するこ
とが出来る。さらに電源ピンを複数設ける必要が無いた
め、半導体パッケージの小型化、低コスト化に寄与する
事が出来る。As described above, according to the present invention, since the lead frame dedicated to the power source is provided around the semiconductor device, it is possible to connect the lead frame of the power source from any pad by the bonding wire. Even a pair of pins can be connected to multiple power pads. This can contribute to stable operation of the semiconductor device. Further, since it is not necessary to provide a plurality of power supply pins, it is possible to contribute to downsizing and cost reduction of the semiconductor package.

【００１２】また、電気信号入力パッドをＶＤＤ、およ
びＶＳＳに接続することにより、半導体装置の一部分の
みを活性化させたり、半導体装置の機能を変更すること
が可能となり、機能確認の為だけに端子を設ける必要が
無くなると言う効果も有する。Further, by connecting the electric signal input pad to VDD and VSS, it is possible to activate only a part of the semiconductor device or change the function of the semiconductor device, and only to confirm the function. There is also an effect that there is no need to provide.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の一実施例を垂直上方向から見た電源専
用リードフレーム付半導体装置の簡略化した平面図。FIG. 1 is a simplified plan view of a semiconductor device with a lead frame for exclusive use of a power source when an embodiment of the present invention is viewed from a vertically upper direction.

【図２】従来の半導体装置の簡略化した平面図。FIG. 2 is a simplified plan view of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

１０１ ・・・ ＶＤＤ電源専用リードフレーム １０２ ・・・ ＶＳＳ電源兼用半導体支持リードフレ
ーム １０３ ・・・ 半導体装置 １０４、１０５、１１０ ・・・ ボンディングワイヤ
ー １０６ ・・・ ＶＳＳ電源パッド １０７ ・・・ ＶＤＤ電源パッド １０８ ・・・ 電気信号伝達用リードフレーム １０９ ・・・ 電気信号入力パッド ２０１ ・・・ ＶＤＤ電源リードフレーム ２０２ ・・・ ＶＳＳ電源リードフレーム ２０３ ・・・ 半導体装置支持用リードフレーム ２０４ ・・・ 半導体装置 ２０５ ・・・ ボンディングワイヤー ２０６ ・・・ ＶＤＤ電源パッド ２０７ ・・・ ＶＳＳ電源パッド ２０８ ・・・ 信号パッド101 ... Lead frame dedicated to VDD power source 102 ... Semiconductor supporting lead frame also serving as VSS power source 103 ... Semiconductor device 104, 105, 110 ... Bonding wire 106 ... VSS power source pad 107 ... VDD power source pad 108 ・ ・ ・ Lead frame for electric signal transmission 109 ・ ・ ・ Electric signal input pad 201 ・ ・ ・ VDD power supply lead frame 202 ・ ・ ・ VSS power supply lead frame 203 ・ ・ ・ Semiconductor device supporting lead frame 204 ・ ・ ・ Semiconductor device 205 ・ ・ ・ Bonding wire 206 ・ ・ ・ VDD power supply pad 207 ・ ・ ・ VSS power supply pad 208 ・ ・ ・ Signal pad

Claims (4)

【特許請求の範囲】[Claims] 【請求項１】半導体装置の組立に使用する金属製リード
フレームにおいて、半導体装置を支える電源兼用半導体
支持リードフレームと電気信号を伝達するためのリード
フレームと電源専用リードフレームとからなり、半導体
装置を支えるリードフレームと半導体装置とを電気的に
接続するボンディングワイヤーによって接続され、電気
信号を伝達するためのリードフレームはボンディングワ
イヤーによって半導体装置のパッド部分と電気的に接続
され、さらに電源専用リードフレームは、電気信号を伝
達するためのリードフレームの垂直上方向に位置し、垂
直上方向から見たとき、半導体装置の周辺を囲むように
輪を形成したリードフレームを配置したことを特徴とす
る電源専用リードフレーム付半導体装置。1. A metal lead frame used for assembling a semiconductor device, comprising a semiconductor supporting lead frame that also serves as a power source for supporting the semiconductor device, a lead frame for transmitting electric signals, and a lead frame dedicated to the power source. The supporting lead frame and the semiconductor device are electrically connected by a bonding wire, and the lead frame for transmitting an electric signal is electrically connected to the pad part of the semiconductor device by the bonding wire. , A power source characterized by arranging a lead frame which is positioned vertically above the lead frame for transmitting an electric signal and formed a ring so as to surround the periphery of the semiconductor device when viewed from above the vertical direction. Semiconductor device with lead frame. 【請求項２】前記電源専用リードフレームが前記電気信
号を伝達するためのリードフレームの垂直下方向に位置
することを特徴とする請求項１記載の電源専用リードフ
レーム付半導体装置。2. The semiconductor device with a lead frame dedicated to a power source according to claim 1, wherein the lead frame dedicated to a power source is positioned vertically below the lead frame for transmitting the electric signal. 【請求項３】前記電源専用リードフレームが前記半導体
装置の１辺以上ととなり合うような棒状としたリードフ
レームを配置したことを特徴とする請求項１記載の電源
専用リードフレーム付半導体装置。3. The semiconductor device with a lead frame dedicated to power supply according to claim 1, wherein a lead frame having a rod shape is arranged such that the lead frame dedicated to the power supply is aligned with at least one side of the semiconductor device. 【請求項４】前記電源専用リードフレーム、または前記
電源兼用半導体支持リードフレームと前記半導体装置の
電源パッド以外のパッドとをボンディングワイヤーによ
って電気的に接続したことを特徴とする請求項１記載の
電源専用リードフレーム付半導体装置。4. The power source according to claim 1, wherein the lead frame dedicated to the power source or the semiconductor supporting lead frame also serving as the power source is electrically connected to a pad other than the power source pad of the semiconductor device by a bonding wire. Semiconductor device with dedicated lead frame.
JP10531296A 1996-04-25 1996-04-25 Semiconductor device with lead frame for power source only Pending JPH09293822A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10531296A JPH09293822A (en) 1996-04-25 1996-04-25 Semiconductor device with lead frame for power source only

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10531296A JPH09293822A (en) 1996-04-25 1996-04-25 Semiconductor device with lead frame for power source only

Publications (1)

Publication Number Publication Date
JPH09293822A true JPH09293822A (en) 1997-11-11

Family

ID=14404197

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10531296A Pending JPH09293822A (en) 1996-04-25 1996-04-25 Semiconductor device with lead frame for power source only

Country Status (1)

Country Link
JP (1) JPH09293822A (en)

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