JPH09293822A - Semiconductor device with lead frame for power source only - Google Patents

Semiconductor device with lead frame for power source only

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Publication number
JPH09293822A
JPH09293822A JP10531296A JP10531296A JPH09293822A JP H09293822 A JPH09293822 A JP H09293822A JP 10531296 A JP10531296 A JP 10531296A JP 10531296 A JP10531296 A JP 10531296A JP H09293822 A JPH09293822 A JP H09293822A
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Prior art keywords
lead frame
semiconductor device
power supply
semiconductor
dedicated
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Pending
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JP10531296A
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Japanese (ja)
Inventor
Hiroyuki Yano
博之 矢野
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Seiko Epson Corp
セイコーエプソン株式会社
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05554Shape in top view being square
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48237Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a die pad of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49175Parallel arrangements
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01004Beryllium [Be]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/078Adhesive characteristics other than chemical
    • H01L2924/07802Adhesive characteristics other than chemical not being an ohmic electrical conductor

Abstract

PROBLEM TO BE SOLVED: To reduce the number of power source pins, increase the number of semiconductor signal pins, and reduce the size and cost of a semiconductor package. SOLUTION: A metal lead frame for use in assembling of a semiconductor device has a lead frame 101 for VDD power source only and a semiconductor supporting lead frame 102 also used for a VSS power source. A semiconductor device 103 is adhered to an insulation adhesive to the latter lead frame 102. The former lead frame 101 is located vertically above an electric signal transmitting lead frame 108 and formed as a ring surrounding the periphery of the semiconductor device 103. Owing to this structure, any semiconductor pad can be connected through a binding wire to the power-only lead frame.

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【発明の属する技術分野】本発明は、半導体装置の組立に使用するリードフレームに関する。 The present invention relates to relates to a lead frame for use in the assembly of the semiconductor device.

【0002】 [0002]

【従来の技術】従来の半導体装置の組立に使用するリードフレームを、図2により説明する。 The lead frame used in the assembly of a conventional semiconductor device will be described with reference to FIG. 図2は、従来の一実施例の半導体装置を示しており、201はVDD電源リードフレーム、202はVSS電源リードフレームであり、この例では電源用として使っている。 Figure 2 shows a semiconductor device of a conventional one embodiment, VDD power lead frames 201, 202 is a VSS power lead frame, in this example using as a power source. 204は半導体装置、203は半導体装置支持用リードフレーム、 204 semiconductor device, 203 a lead frame for a semiconductor device substrate,
205はボンディングワイヤー、206はVDD電源パッド、207はVSS電源パッドであり、半導体装置2 205 bonding wire, 206 VDD power supply pad 207 is VSS power supply pads, the semiconductor device 2
04は半導体支持用リードフレームに接着し固定してある。 04 are bonded and fixed to the semiconductor support for the lead frame. また、VDD電源リードフレーム201はボンディングワイヤー205によってVDD電源パッド206に電気的に接続している。 Also electrically connected to the VDD power supply pads 206 by VDD power lead frame 201 has a bonding wire 205. これにより、半導体装置204 Thus, the semiconductor device 204
にVDD電源を供給している。 It is supplying VDD power to. 同様にVSS電源リードフレーム202はボンディングワイヤー205によって、VSS電源パッド207に電気的に接続される。 Similarly the VSS power lead frame 202 is a bonding wire 205 is electrically connected to the VSS power supply pad 207. これによりVSS電源を半導体装置204に供給している。 Thereby to supply VSS power to the semiconductor device 204. 209は電気信号伝達用リードフレーム、208は信号パッドであり、電気信号伝達用リードフレーム20 209 lead frame for electrical signal transmission, 208 is a signal pad, the electrical signal transmitting lead frame 20
9はボンデイングワイヤー205によって信号パッド2 9 signal pads 2 by bonding wires 205
08に電気的に接続されている。 It is electrically connected to the 08. これにより、電気信号を半導体装置204に入力あるいは出力する事が出来る。 Thus, electrical signals may be input or output to the semiconductor device 204.

【0003】 [0003]

【発明が解決しようとする課題】上記の従来の半導体装置の組立に使用するリードフレームは、一つの電源パッドに対して一つのリードフレームを必要としていたため、電源ピンが電源パッド分だけ必要となり、ピン数の増加、半導体パッケージの大型化、組立コストの増加をまねくという課題を有する。 A lead frame for use in the assembly of the 0007] The above conventional semiconductor device, since that required one lead frame for one of the power supply pads, required power pin only power supply pad min has increased the number of pins, large size of the semiconductor package, the problem of causing an increase in assembly cost.

【0004】また、半導体装置を安定して動作させるためにはどうしても複数電源ピンを設ける必要が生じ、電源ピン数を減らすことが難しかった。 [0004] In order to stably operate the semiconductor device is required to just providing a plurality of power supplies pins occurs, it is difficult to reduce the number of power supply pins.

【0005】そこで、本発明はこのような課題を解決するもので、その目的とするところは、電源ピン数を増加させる事なく、半導体装置を安定動作させるところにある。 [0005] The present invention is intended to solve such problems, it is an object without increasing the number of power pins, there is to allow stable operation of the semiconductor device.

【0006】 [0006]

【課題を解決するための手段】本発明の電源専用リードフレーム付半導体装置は、半導体装置の組立に使用する金属製リードフレームにおいて、半導体装置を支える電源兼用半導体支持リードフレームと電気信号を伝達するためのリードフレームと電源専用リードフレームとからなり、半導体装置を支えるリードフレームと半導体装置とを電気的に接続するボンディングワイヤーによって接続され、電気信号を伝達するためのリードフレームはボンディングワイヤーによって半導体装置のパッド部分と電気的に接続され、さらに電源専用リードフレームは、 Means for Solving the Problems] power only lead frame with the semiconductor device of the present invention, the metal lead frame used for assembly of semiconductor devices, transmitting power supply combined semiconductor supporting lead frame and an electric signal for supporting the semiconductor device It consists of a lead frame and a power supply dedicated lead frame for, are connected by a bonding wire electrically connecting the lead frame and the semiconductor device to support the semiconductor device, the lead frame for transmitting an electric signal semiconductor device by bonding wires a pad portion and electrically connected to the further supply only the lead frame,
電気信号を伝達するためのリードフレームの垂直上方向に位置し、半導体装置の周辺を囲むように輪を形成したリードフレームを配置したことを特徴とする。 Located vertically upward of the lead frame for transmitting electrical signals, characterized in that a lead frame to form a loop so as to surround the periphery of the semiconductor device.

【0007】 [0007]

【発明の実施の形態】以下、本発明の一実施例を図面により説明する。 BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, will be explained by an embodiment of the present invention with reference to the accompanying drawings.

【0008】図1は,本発明の一実施例における電源専用リードフレーム付半導体装置を示しており、101はVDD電源専用リードフレーム、108は電気信号伝達用リードフレーム、102はVSS電源兼用半導体支持リードフレーム、103は半導体装置であり、半導体装置103はVSS電源兼用半導体支持リードフレーム1 [0008] Figure 1 shows a semiconductor device with a power supply only the lead frame in an embodiment of the present invention, 101 VDD power supply dedicated leadframe 108 lead frame for electrical signal transmission, 102 VSS power combined semiconductor support lead frame, 103 is a semiconductor device, the semiconductor device 103 is VSS power combined semiconductor supporting lead frame 1
02の上に絶縁性の接着剤によつて絶縁するように張り付けてある。 By the insulating adhesive on top of the 02 go-between are stuck to insulate. また、VDD電源専用リードフレーム10 In addition, VDD power supply dedicated lead frame 10
1は、電気信号伝達用リードフレーム108の垂直上方向に位置し、半導体装置103の周辺を囲むように輪を形成して配置されている。 1 is positioned vertically upward of the electrical signal transmitting lead frame 108 are disposed to form a ring so as to surround the periphery of the semiconductor device 103. さらに図1に示したVDD電源専用リードフレーム101の右上、左下へのびる部分はVDD電源ピンとして半導体パッケージの外に出され、なおかつ、VDD電源専用リードフレーム101を支える役割を果たす。 Furthermore the upper right of the VDD power supply dedicated lead frame 101 shown in FIG. 1, a portion extending to the bottom left is issued outside of the semiconductor package as VDD supply pins, yet serve to support the VDD power supply dedicated lead frame 101. 107はVDD電源パッド、10 107 VDD power supply pad, 10
4はボンディングワイヤーであり、VDD電源パッド1 4 is a bonding wire, VDD power supply pad 1
07はボンディングワイヤー104によってVDD電源専用リードフレーム101に電気的に接続される。 07 is electrically connected to the VDD power supply dedicated lead frame 101 by bonding wires 104. これにより半導体装置103にVDD電源が供給される。 This VDD power is supplied to the semiconductor device 103 by. 1
06はVSS電源パッド、105はボンディングワイヤーであり、VSS電源パッド106はボンディングワイヤー105によって、VSS電源兼用半導体支持リードフレーム102に電気的に接続される。 06 VSS power supply pads 105 are bonding wires, the VSS power supply pads 106 bonding wires 105 are electrically connected to the VSS power supply combined semiconductor supporting lead frame 102. これにより、半導体装置103にVSS電源が供給される。 Thus, VSS power is supplied to the semiconductor device 103. 半導体装置103はVSS電源パッド106及び、VDD電源パッド107が多くあればあるほど安定動作し有利になる。 The semiconductor device 103 and VSS power supply pad 106, becomes a certain extent stable operation advantageous if many VDD power supply pad 107.
前述した構造にしたためVDD電源専用リードフレーム101およびVSS電源兼用半導体支持リードフレーム102に対して複数ボンディングでき、なおかつ他のボンディングワイヤーと接触しないように接続することが出来る。 Can multiple bonding for VDD supply only the lead frame 101 and the VSS power supply combined semiconductor supporting lead frame 102 due to the above structure, it is possible yet to connect so as not to contact with other bonding wires.

【0009】また、109は電気信号入力パッドであり、電気信号入力パッド109を電気信号伝達用リードフレームではなく、VDD電源専用リードフレーム10 Further, 109 is an electrical signal input pad, an electrical signal input pad 109 rather than electrical signal transmitting lead frame, VDD power supply only lead frame 10
1およびVSS電源兼用半導体支持リードフレーム10 1 and VSS power combined semiconductor supporting lead frame 10
2へボンディングワイヤー110を使って接続することにより、半導体装置の一部分のみを活性化させたり、半導体装置の機能を変更するのに使用することができる。 By connecting with the bonding wire 110 to 2, it is possible to use only a portion of the semiconductor device or activated, to change the function of the semiconductor device.

【0010】なお、本実施例ではVDD電源専用リードフレーム101の形状が半導体装置の周辺を囲むように輪を形成しているが、半導体装置の1辺以上ととなり合うような棒状としたVDD電源専用リードフレームでも、同様の効果を得ることが出来る。 [0010] Although this embodiment forms a circle so that the shape of the VDD power supply dedicated lead frame 101 surrounding the periphery of the semiconductor device, VDD power supply has a rod like adjacent to one side or the semiconductor device be a dedicated lead frame, it is possible to obtain the same effect.

【0011】 [0011]

【発明の効果】以上述べたように、本発明によれば半導体装置の周囲に電源専用リードフレームを備えたことにより、どのパッドからでもボンディングワイヤーによって電源のリードフレームに接続することができ、電源ピンが一対であっても複数の電源パッドに接続することが出来る。 As described above, according to the present invention, by providing power only lead frame around the semiconductor device according to the present invention, it can be connected by bonding wires from any pads to the power lead frame, the power source pins can be connected a pair in a plurality of power supply pads. これにより半導体装置の安定動作に寄与することが出来る。 Thus it is possible to contribute to a stable operation of the semiconductor device. さらに電源ピンを複数設ける必要が無いため、半導体パッケージの小型化、低コスト化に寄与する事が出来る。 Moreover since it is not necessary to provide a plurality of power supply pins, miniaturization of the semiconductor package, it is possible to contribute to cost reduction.

【0012】また、電気信号入力パッドをVDD、およびVSSに接続することにより、半導体装置の一部分のみを活性化させたり、半導体装置の機能を変更することが可能となり、機能確認の為だけに端子を設ける必要が無くなると言う効果も有する。 Further, by connecting the electric signal input pad VDD, and VSS, or by activating only a portion of the semiconductor device, it is possible to change the function of the semiconductor device, the terminal only for the function confirmation also has the effect to say that it is not necessary to provide a.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】本発明の一実施例を垂直上方向から見た電源専用リードフレーム付半導体装置の簡略化した平面図。 [1] simplified plan view of the power supply dedicated semiconductor device with lead frames viewed one embodiment the vertically upward of the present invention.

【図2】従来の半導体装置の簡略化した平面図。 [Figure 2] simplified plan view of a conventional semiconductor device.

【符号の説明】 DESCRIPTION OF SYMBOLS

101 ・・・ VDD電源専用リードフレーム 102 ・・・ VSS電源兼用半導体支持リードフレーム 103 ・・・ 半導体装置 104、105、110 ・・・ ボンディングワイヤー 106 ・・・ VSS電源パッド 107 ・・・ VDD電源パッド 108 ・・・ 電気信号伝達用リードフレーム 109 ・・・ 電気信号入力パッド 201 ・・・ VDD電源リードフレーム 202 ・・・ VSS電源リードフレーム 203 ・・・ 半導体装置支持用リードフレーム 204 ・・・ 半導体装置 205 ・・・ ボンディングワイヤー 206 ・・・ VDD電源パッド 207 ・・・ VSS電源パッド 208 ・・・ 信号パッド 101 ... VDD supply only the lead frame 102 ... VSS power combined semiconductor supporting lead frame 103 ... semiconductor device 104,105,110 ... bonding wire 106 ... VSS power supply pads 107 ... VDD power supply pads 108 ... electric signal transmitting lead frame 109 ... electric signal input pad 201 ... VDD power lead frame 202 ... VSS power lead frame 203 ... semiconductor device supporting lead frame 204 ... semiconductor device 205 ... bonding wire 206 ... VDD power supply pads 207, ... VSS power supply pads 208 ... signal pads

Claims (4)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】半導体装置の組立に使用する金属製リードフレームにおいて、半導体装置を支える電源兼用半導体支持リードフレームと電気信号を伝達するためのリードフレームと電源専用リードフレームとからなり、半導体装置を支えるリードフレームと半導体装置とを電気的に接続するボンディングワイヤーによって接続され、電気信号を伝達するためのリードフレームはボンディングワイヤーによって半導体装置のパッド部分と電気的に接続され、さらに電源専用リードフレームは、電気信号を伝達するためのリードフレームの垂直上方向に位置し、垂直上方向から見たとき、半導体装置の周辺を囲むように輪を形成したリードフレームを配置したことを特徴とする電源専用リードフレーム付半導体装置。 1. A metal lead frame used for assembly of semiconductor devices consists of a lead frame and a power supply dedicated lead frame for transmitting power supply combined semiconductor supporting lead frame and an electric signal for supporting the semiconductor device, the semiconductor device are connected by a bonding wire electrically connecting the lead frame and the semiconductor device to support, the lead frame for transmitting an electric signal is connected to the pad portion and electrically semiconductor device by bonding wires, further power dedicated lead frame located vertically upward of the lead frame for transmitting electrical signals, when viewed from the vertical upward direction, the power source dedicated characterized in that a lead frame to form a loop so as to surround the periphery of the semiconductor device semiconductor device with a lead frame.
  2. 【請求項2】前記電源専用リードフレームが前記電気信号を伝達するためのリードフレームの垂直下方向に位置することを特徴とする請求項1記載の電源専用リードフレーム付半導体装置。 Wherein said power supply dedicated leadframe supply only the lead frame with the semiconductor device according to claim 1, wherein the located vertically downward of the lead frame for transmitting the electrical signal.
  3. 【請求項3】前記電源専用リードフレームが前記半導体装置の1辺以上ととなり合うような棒状としたリードフレームを配置したことを特徴とする請求項1記載の電源専用リードフレーム付半導体装置。 Wherein the power source dedicated leadframe supply only the lead frame with the semiconductor device according to claim 1, wherein the rod-like and to be placing the lead frame, such as adjacent to one side or the semiconductor device.
  4. 【請求項4】前記電源専用リードフレーム、または前記電源兼用半導体支持リードフレームと前記半導体装置の電源パッド以外のパッドとをボンディングワイヤーによって電気的に接続したことを特徴とする請求項1記載の電源専用リードフレーム付半導体装置。 Wherein said power supply only lead frame or power according to claim 1, wherein the electrically connected by the power supply combined semiconductor supporting lead frame and the semiconductor device power supply pad than the pad and the bonding wire, semiconductor device with a dedicated lead frame.
JP10531296A 1996-04-25 1996-04-25 Semiconductor device with lead frame for power source only Pending JPH09293822A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10531296A JPH09293822A (en) 1996-04-25 1996-04-25 Semiconductor device with lead frame for power source only

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10531296A JPH09293822A (en) 1996-04-25 1996-04-25 Semiconductor device with lead frame for power source only

Publications (1)

Publication Number Publication Date
JPH09293822A true true JPH09293822A (en) 1997-11-11

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DE10124970A1 (en) * 2001-05-21 2002-11-28 Infineon Technologies Ag Electronic component has a semiconductor chip mounted on a semiconductor chip connecting plate in the center of a flat lead frame of the support
US6798046B1 (en) * 2002-01-22 2004-09-28 Amkor Technology, Inc. Semiconductor package including ring structure connected to leads with vertically downset inner ends
US6833609B1 (en) 1999-11-05 2004-12-21 Amkor Technology, Inc. Integrated circuit device packages and substrates for making the packages
US6847099B1 (en) 2003-02-05 2005-01-25 Amkor Technology Inc. Offset etched corner leads for semiconductor package
US7187065B2 (en) 2004-09-17 2007-03-06 Fujitsu Limited Semiconductor device and semiconductor device unit
WO2013044838A1 (en) * 2011-09-30 2013-04-04 Mediatek Inc. Semiconductor package
US8691632B1 (en) 2002-11-08 2014-04-08 Amkor Technology, Inc. Wafer level package and fabrication method
US8900995B1 (en) 2010-10-05 2014-12-02 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof
US8937381B1 (en) 2009-12-03 2015-01-20 Amkor Technology, Inc. Thin stackable package and method
US8981572B1 (en) 2011-11-29 2015-03-17 Amkor Technology, Inc. Conductive pad on protruding through electrode semiconductor device
US9048298B1 (en) 2012-03-29 2015-06-02 Amkor Technology, Inc. Backside warpage control structure and fabrication method
US9082833B1 (en) 2011-01-06 2015-07-14 Amkor Technology, Inc. Through via recessed reveal structure and method
US9129943B1 (en) 2012-03-29 2015-09-08 Amkor Technology, Inc. Embedded component package and fabrication method
US9159672B1 (en) 2010-08-02 2015-10-13 Amkor Technology, Inc. Through via connected backside embedded circuit features structure and method
US9324614B1 (en) 2010-04-06 2016-04-26 Amkor Technology, Inc. Through via nub reveal method and structure
US9691734B1 (en) 2009-12-07 2017-06-27 Amkor Technology, Inc. Method of forming a plurality of electronic component packages
US9704725B1 (en) 2012-03-06 2017-07-11 Amkor Technology, Inc. Semiconductor device with leadframe configured to facilitate reduced burr formation
US9852966B2 (en) 2011-09-30 2017-12-26 Mediatek Inc. Semiconductor package
US9978695B1 (en) 2011-01-27 2018-05-22 Amkor Technology, Inc. Semiconductor device including leadframe with a combination of leads and lands and method

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US6833609B1 (en) 1999-11-05 2004-12-21 Amkor Technology, Inc. Integrated circuit device packages and substrates for making the packages
US6774479B2 (en) 2001-05-21 2004-08-10 Infineon Technologies Ag Electronic device having a semiconductor chip on a semiconductor chip connection plate and a method for producing the electronic device
DE10124970B4 (en) * 2001-05-21 2007-02-22 Infineon Technologies Ag Electronic component having a semiconductor chip on a semiconductor chip connection board, system unit and methods for their preparation
DE10124970A1 (en) * 2001-05-21 2002-11-28 Infineon Technologies Ag Electronic component has a semiconductor chip mounted on a semiconductor chip connecting plate in the center of a flat lead frame of the support
US6798046B1 (en) * 2002-01-22 2004-09-28 Amkor Technology, Inc. Semiconductor package including ring structure connected to leads with vertically downset inner ends
US8691632B1 (en) 2002-11-08 2014-04-08 Amkor Technology, Inc. Wafer level package and fabrication method
US9406645B1 (en) 2002-11-08 2016-08-02 Amkor Technology, Inc. Wafer level package and fabrication method
US9054117B1 (en) 2002-11-08 2015-06-09 Amkor Technology, Inc. Wafer level package and fabrication method
US8952522B1 (en) 2002-11-08 2015-02-10 Amkor Technology, Inc. Wafer level package and fabrication method
US9871015B1 (en) 2002-11-08 2018-01-16 Amkor Technology, Inc. Wafer level package and fabrication method
US6847099B1 (en) 2003-02-05 2005-01-25 Amkor Technology Inc. Offset etched corner leads for semiconductor package
US7187065B2 (en) 2004-09-17 2007-03-06 Fujitsu Limited Semiconductor device and semiconductor device unit
US8937381B1 (en) 2009-12-03 2015-01-20 Amkor Technology, Inc. Thin stackable package and method
US9691734B1 (en) 2009-12-07 2017-06-27 Amkor Technology, Inc. Method of forming a plurality of electronic component packages
US9324614B1 (en) 2010-04-06 2016-04-26 Amkor Technology, Inc. Through via nub reveal method and structure
US9159672B1 (en) 2010-08-02 2015-10-13 Amkor Technology, Inc. Through via connected backside embedded circuit features structure and method
US8900995B1 (en) 2010-10-05 2014-12-02 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof
US9082833B1 (en) 2011-01-06 2015-07-14 Amkor Technology, Inc. Through via recessed reveal structure and method
US9978695B1 (en) 2011-01-27 2018-05-22 Amkor Technology, Inc. Semiconductor device including leadframe with a combination of leads and lands and method
WO2013044838A1 (en) * 2011-09-30 2013-04-04 Mediatek Inc. Semiconductor package
CN103140923A (en) * 2011-09-30 2013-06-05 联发科技股份有限公司 The semiconductor package
US8941221B2 (en) 2011-09-30 2015-01-27 Mediatek Inc. Semiconductor package
US9852966B2 (en) 2011-09-30 2017-12-26 Mediatek Inc. Semiconductor package
US8981572B1 (en) 2011-11-29 2015-03-17 Amkor Technology, Inc. Conductive pad on protruding through electrode semiconductor device
US9431323B1 (en) 2011-11-29 2016-08-30 Amkor Technology, Inc. Conductive pad on protruding through electrode
US9947623B1 (en) 2011-11-29 2018-04-17 Amkor Technology, Inc. Semiconductor device comprising a conductive pad on a protruding-through electrode
US10090228B1 (en) 2012-03-06 2018-10-02 Amkor Technology, Inc. Semiconductor device with leadframe configured to facilitate reduced burr formation
US9704725B1 (en) 2012-03-06 2017-07-11 Amkor Technology, Inc. Semiconductor device with leadframe configured to facilitate reduced burr formation
US9129943B1 (en) 2012-03-29 2015-09-08 Amkor Technology, Inc. Embedded component package and fabrication method
US10014240B1 (en) 2012-03-29 2018-07-03 Amkor Technology, Inc. Embedded component package and fabrication method
US9048298B1 (en) 2012-03-29 2015-06-02 Amkor Technology, Inc. Backside warpage control structure and fabrication method

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