JP2681937B2 - Flip flop - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit flip-flop, and more particularly to a master-slave flip-flop with a selector that selects and latches an arbitrary signal from a plurality of input signals. . [Prior Art] Conventionally, in this type of master-slave flip-flop, a signal having the same logical amplitude as the input / output signal of the flip-flop has been used as a transmission signal from the master latch to the slave latch. FIG. 2 is a diagram showing an example of a conventional flip-flop. In Fig. 2, NPNs with their emitters coupled to each other
Transistors 101 and 102, NPN transistors 103 and 104,
And NPN type transistors 105 and 106 constitute a latch on the master side, and their emitters are coupled to each other. NPN type transistors 107 and 108, NPN type transistors 109 and 110, and N
NPN type transistors 113, 114 and 115, and NPN type transistors 116, 117 and 1 in which the slave side latch is configured by the PN type transistors 111 and 112 and the emitters of the slave side are coupled to each other.
The selector 18 is constituted by 18. Transistors 101 and 102 have their emitters coupled to each other to form a first emitter coupling section 120, and
The emitters of 104 are coupled to each other to form a second emitter coupling section 121. The collector of the transistor 105 is connected to the first emitter coupling section 120, and the collector of the transistor 106 is connected to the second emitter coupling section 121. The transistors 105 and 106 have their emitters coupled to each other to form a third emitter coupling section 122. The collector of the transistor 101, the collector of the transistor 103 and the base of the transistor 104 are coupled to each other to form a first collector coupling section 130, and the collector of the transistor 102, the collector of the transistor 104 and the transistor 103
Bases are joined together to form a second collector junction 131
Is formed. One terminal of the resistor 140 is connected to the first collector coupling portion 130, and the other terminal of the resistor 140 is connected to the first power supply potential 170. One terminal of the resistor 141 is connected to the second collector coupling portion 131, and the other terminal of the resistor 141 is connected to the first power supply potential 170. One terminal of the constant current source 160 is connected to the third emitter coupling section 122, and the other terminal of the constant current source 160 is connected to the second power source potential 171 lower than the first power source potential 170. Then, a current having a constant value I ₁ flows from the third emitter coupling portion 122 toward the second power supply potential 171. Transistors 101, 102, 103, 10 connected as described above
A master latch circuit 195 is constituted by 4, 105, 106, resistors 140, 141 and constant current source 160. This master latch circuit includes a first emitter coupling unit 1 between the first power supply potential 170 and the second power supply potential 171.
20 and the third emitter coupling part 122, or the second emitter coupling part 121 and the third emitter coupling part 122, because of the structure having the two-stage emitter coupling part,
Vertical two-stage emitter coupled logic (Emitter
Coupled Logic: hereinafter referred to as ECL) circuit. The master latch circuit 195 is supplied with input data D _S to the base of the transistor 101, the DC potential V _R1 corresponding to the middle of the logical amplitude of the input data D _S to the first reference potential 172 connected to the base of the transistor 102 Is supplied to the clock terminal 190 connected to the base of the transistor 105, and the second reference potential 173 connected to the base of the transistor 106 is supplied with a DC voltage corresponding to the middle of the logical amplitude of the clock signal X. V _R2 is being supplied. Next, the operation of the master latch circuit 195 will be described. Now, when the clock signal X supplied to the clock terminal 190 is at a high level compared to the second reference potential V _R2 , the transistor 105 is turned on, the transistor 106 is turned off, and the current I ₁ is It flows through 105 to the constant current source 160. At this time, assuming that the input data D _S supplied to the base of the transistor 101 is at a high level compared with the first reference potential V _R1 supplied to the base of the transistor 102, the transistor 101 is on and the transistor 102 is on.
Is turned off, and the current I ₁ flows through the transistor 101 to the collector of the transistor 105. That is, the current I ₁
Is a resistor 140, a transistor 101,
It flows through the transistor 105 and the constant current source 160 in order to the second power supply potential 171. Therefore, the first collector coupling section 130 on the current path becomes low level, and the second collector coupling section 131 not on the current path becomes high level. Here, the base of the transistor 104 is in the low level state because it is connected to the first collector coupling section 130, and the base of the transistor 103 is in the high level state because it is connected to the second collector coupling section 131. Is in a state. When the clock signal X falls from the high level to the low level, the base potential of the transistor 106 connected to the second reference potential V _R2 becomes higher than the base potential of the transistor 105, so that the transistor 105 is turned off,
The transistor 106 is turned on, and the current I ₁ flowing through the transistor 105 is switched so as to flow through the transistor 106. At this time, since the base of the transistor 103 was at the high level and the base of the transistor 104 was at the low level, the transistor 103 was turned on, the transistor 104 was turned off, and the current I ₁ flows through the transistor 103. That is,
Current I ₁ is from the first power supply potential 170 to resistor 140, transistor 1
03, transistor 106, and constant current source 160 in order
Flows into the power supply potential 171 of. Therefore, the first collector coupling section 130 has a low level and the second collector coupling section 131 has a low level.
Is latched at a high level. Input data D _S supplied to the base of transistor 101
Is at a low level compared to the first reference potential V _R1 supplied to the base of the transistor 102, the current I ₁ is a resistance from the first power source potential 170 when the clock signal X is at a high level. 141 transistor 102, transistor
The second collector coupling part 131 on the current path is at a low level, and the first collector coupling part 130 not on the current path is at a high level. . At this time, the base of the transistor 104 connected to the first collector coupling unit 130 is at the high level,
The base of the transistor 103 connected to the collector coupling unit 131 of the clock signal X is in the low level state, and the clock signal X
When I falls from the high level to the low level, the current I ₁ becomes the first
Since the current flows from the power supply potential 170 through the resistor 141, the transistor 104, the transistor 106, and the constant current source 160 in order, a high level is applied to the first collector coupling part 130 and a low level is applied to the second collector coupling part 131. Latched. As described above, in the master latch circuit 195, when the clock signal X falls from the high level to the low level, the negative logic level of the input data D _S is supplied to the first collector coupling unit 130 and the second collector common unit 131 is supplied. Is latched at the positive logic level of the input data D _S. The slave latch circuit 196 is a vertical two-stage ECL circuit having the same circuit configuration as the master latch circuit. That is, the transistors 107, 108, 10 of the slave latch circuit 196
9,110,111,112, resistors 142,143, and constant current source 161 are transistors 101,102,103,1 of the master latch circuit 195, respectively.
04, 105, 106, resistors 140, 141, and constant current source 160.
4, the fifth and sixth emitter coupling portions 123, 124, 125, and the third and fourth
The collector coupling portions 132 and 133 of the above correspond to the first, second and third emitter coupling portions 120, 121 and 122 and the first and second collector coupling portions 130 and 131 of the master latch circuit 195, respectively. Further, an emitter follower made up of a transistor 119 and a resistor 145 is connected to the output section of the slave latch circuit 196, and the emitter follower output is output to the flip-flop output signal D _OUT.
And The slave latch circuit 196 also performs the same latching operation as the master latch circuit 195, and the third collector coupling unit 132 receives the negative logic level of the input data D _M output from the master latch circuit 195 and the fourth collector coupling unit 133. Input data to D
Latch the positive logic level of _M. However, in the master latch circuit 195, the clock signal X is input to the base of the transistor 105 and the second reference potential V _R2 is input to the base of the transistor 106, whereas in the slave latch circuit 196, it corresponds to the transistor 105. Transistor
The second reference potential V _R2 is input to the base of 111, and the clock signal X is input to the base of the transistor 112 corresponding to the transistor 106, and the connection relationship between the clock signal X and the second reference potential V _R2 is reversed. It has become. Therefore, the master latch circuit 195 latches the data when the clock signal X falls from the high level to the low level, whereas the slave latch circuit 196 latches the data when the clock signal X rises from the low level to the high level. To latch. The selector circuit 197 has a first gate circuit composed of transistors 113, 114, 115 and constant current sources 162 whose emitters are coupled to each other, and a transistor whose emitters are coupled to each other.
The second gate circuit includes 116, 117, 118 and a constant current source 163. Transistors 113, 114, and 115 have their emitters coupled to each other to form an emitter coupling section 126.
The collectors of 13,114 are coupled and connected to the first power supply potential 170, and the collector of the transistor 115 is connected to the first power supply potential 170 via the resistor 144. Emitter coupling 1
One terminal of the constant current source 162 is connected to 26, and the constant current source 1
The other terminal of 62 is connected to the second power supply potential 171, and a current of a constant value I ₁ flows from the emitter coupling section 126 toward the second power supply potential 171. This circuit operates from the first power supply potential 170 to the second power supply potential 1
Since there is one stage of the emitter coupling section 126 up to 71, the master latch circuit 195 and the slave latch circuit 196
Compared to the vertical two-stage ECL circuit, it is called a one-stage ECL circuit. The second gate circuit is a one-stage ECL circuit having the same circuit configuration as the first gate circuit. That is, the transistors 116, 117, 118 of the second gate circuit and the constant current source 163.
Are transistors 113, 114, 11 of the first gate circuit, respectively.
5 and the constant current source 162, and the emitter coupling part 127 is the first
This corresponds to the emitter coupling part 126 of the gate circuit. The collector of the transistor 118 of the second gate circuit is coupled to the collector of the transistor 115 of the first gate circuit, and the resistor 144 is connected between the first gate circuit and the second gate circuit.
To share. The operation of the selector circuit 197 will be described. The base of the transistor 113 of the first gate circuit has the first
Input data D ₁ is supplied to the base of the transistor 114 to select the _first input data D ₁
Is supplied. Second gate circuit transistor 11
6 based second input data D ₂ is supplied to the select signal S ₂ for selecting the second input data D ₂ to the base of the transistor 117 is supplied. The bases of the transistors 115 and 118 are supplied with the first input data D ₁ , the second input data D ₂ , and the DC potential V _R2 corresponding to the middle of the logical amplitude of the select signals S ₁ and S _2. ing. Now, consider a case where the select signal S ₁ is at a low level and the select signal S ₂ is at a high level as compared with the second reference potential V _R2 . At this time, in the second gate circuit, the transistor
Since the base potential of 117 is higher than that of the transistor 118 supplied with the second reference potential V _R2 ,
The transistor 117 is turned on and the transistor 118 is turned off. Therefore, regardless of whether the input data D ₂ supplied to the base of the transistor 116 is high level or low level, the current I ₁ is constant from the first power supply potential 170 through a branch of the transistor 117. The current flows to the current source 163, and the transistor 118 is turned off. At this time, in the first gate circuit, a transistor
Since the base potential of 114 is lower than the base potential of the transistor 115 supplied with the second reference potential V _R2 , the transistor 114 is turned off, and the current I ₁ is
The current flows through the transistor 13 or the transistor 115 to the constant current source 162, and which of the current flows is determined by the _first input data D ₁ supplied to the base of the transistor 113. That is, the first input data D ₁ is the second reference potential
If the level is lower than V _R2 , the transistor 113 is off,
Transistor 115 is turned on, current I ₁ is the transistor 1
If the first input data D ₁ is higher than the second reference potential V _R2 , the transistor 113 is turned on, the transistor 115 is turned off, and the current I ₁ flows through the transistor 113. When the first input data D ₁ is low level and the current I ₁ flows through the transistor 115, the transistors 115 and 11
The collector coupling part 134 of 8 becomes low level. Also, the first
Input data D ₁ of high level and current I ₁ of transistor 11
When flowing through 3, no current flows in the transistor 115 of the first gate circuit or the transistor 118 of the second gate circuit, so that the collector coupling portion 134 becomes high level. As described above, when the select signal S ₁ is at the low level and the select signal S ₂ is at the high level, the logical value of the first input data D ₁ is selected and appears in the collector coupling section 134, which is the selector circuit 197. Output D _S. When the select signal S ₁ is high level and the select signal S ₂ is low level, the operation of the first gate circuit and the second gate circuit when the select signal S ₁ is low level and the select signal S ₂ is high level Since the operations of (1) and (2) are switched, the logical value of the second input data D ₂ is selected and appears in the collector coupling unit 134, and this becomes the output D _{S of the} selector circuit 197. The flip-flop illustrated in FIG. 2 is composed of the master latch circuit 195, the slave latch circuit 196, and the selector circuit 197 as described above.
In the collector coupling section 134, _{one of} the input data D ₁ or D ₂ selected by the select signals S ₁ and S ₂ at
This is the master latch circuit 195 and slave latch circuit 196.
It is latched by a master-slave flip-flop consisting of. [Problems to be Solved by the Invention] In the above-described conventional flip-flop, the transmission signal from the master latch circuit 195 to the slave latch circuit 196 is
A signal having the same logical amplitude as the input / output signal to / from the flip-flop was used. That is, assuming that the resistance value of the resistor 141 is R, the logical amplitude V _l of the output signal D _M of the master latch circuit 195 is the current value I ₁ to V _l I ₁ R of the constant current source. The value of _l is the input signal D _{1 of} the flip-flop,
It was made to have the same value as D ₂ , S ₁ , S ₂ , X and the output signal D _OUT . Therefore, when the output of the master latch circuit is at a high level, the base potential of the input transistor 107 of the slave latch circuit becomes higher than the collector potential and the transistor 107 is saturated, so that the signal propagation delay time of the slave latch circuit is large, There is a drawback that it hinders high-speed operation as a flip-flop. [Means for Solving Problems] A flip-flop according to the present invention includes at least a first and a second transistor, and a first emitter coupling section in which the emitters of the first and the second transistor are coupled to each other. A second emitter coupling part including third and fourth transistors, wherein emitters of the third and fourth transistors are coupled to each other, and a fifth emitter coupling part having a collector connected to the first emitter coupling part. Three emitter junctions of a third emitter junction including a transistor and a sixth transistor having a collector connected to the second emitter junction, wherein the emitters of the fifth and sixth transistors are coupled to each other And a collector of the first transistor, a collector of the third transistor and a base of the fourth transistor are connected to each other. One collector coupling part, two collector coupling parts of a second collector coupling part in which the collector of the second transistor, the collector of the fourth transistor and the base of the third transistor are connected to each other. , A common collector resistor part including first and second resistors having one ends connected to the first and second collector coupling parts, respectively, and the other ends of the first and second resistors being connected to each other. A first resistor having one end connected to the common collector resistor portion and one end connected to the third emitter coupling portion.
Constant current source of the third resistor, the constant power source connected to the other end of the third resistor from the first power source potential to a second power source potential connected to the other end of the first constant current source A first latch circuit for flowing a current to perform a differential operation; and a seventh and an eighth transistor.
A fourth emitter coupling part in which the emitters of the transistors are coupled to each other, and a ninth and a tenth transistor,
A fifth emitter coupling section in which the emitters of the ninth and tenth transistors are coupled to each other, an eleventh transistor having a collector connected to the fourth emitter coupling section, and a collector in the fifth emitter coupling section. And a twelfth transistor connected to each other, wherein the emitters of the eleventh and twelfth transistors have three emitter coupling parts of a sixth emitter coupling part, and the collector of the seventh transistor And a third collector coupling part in which the collector of the ninth transistor and the base of the tenth transistor are connected to each other, the collector of the eighth transistor, the collector of the tenth transistor, and the ninth transistor Has two collector coupling parts, the bases of which are connected to each other, and the third and fourth collector coupling parts.
One end is connected to each collector coupling part of the other, and the other end has fourth and fifth resistors commonly connected to the first power supply potential, and one end is connected to the sixth emitter coupling part, A second latch circuit having a second constant current source whose other end is connected to the second power supply potential and having both positive logic output and negative logic output of the first latch circuit as balanced inputs; , A plurality of transistors whose emitters are coupled to each other and whose collectors are directly or via resistors connected to the first power supply potential, and a constant current source is coupled to a point where the emitters of the plurality of transistors are coupled to each other The gate circuit includes at least two gate circuits that perform a differential operation by flowing a constant current toward the second power supply potential, and select one of the inputs of the gate circuits to select the first circuit. The input to the latch circuit And a shifter circuit configured to shift only a propagation signal from the first latch circuit to the second latch circuit to a low DC level with a logical amplitude smaller than the logical amplitude of an input / output signal with the outside of the circuit. It is characterized in that it is operated as a signal. Embodiment Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing a configuration of a flip-flop according to an embodiment of the present invention. The circuit shown in FIG. 1 is a flip-flop according to the prior art shown in FIG.
40 and the terminal of the resistor 141 on the side connected to the first power supply potential 170 are not directly connected to the first power supply potential 170, but these terminals are coupled to each other to form the common collector resistance section 50,
After connecting the third resistor 42 to this, the first power supply potential 170
To the slave latch circuit 196 transistor 1
The one in which the first reference potential 172 is input to the base of 08 is the negative logic output signal D _{M of the} master latch circuit 95.
Is input. The signal D _M connected to the base of the transistor 8 of the slave latch circuit 96 changes to a high level or a low level unlike the case of the first reference potential V _R1 , but a signal which is always input to the base of the transistor 7. Since the inverted signal of D _M is input, the mechanism of the latch operation is the same as that described in the prior art. Further, the circuit operation of the master latch circuit 95 and the selector circuit 97, and the operation of all of them as a flip-flop are the same as those described in the prior art, and therefore the description thereof is omitted here. In the flip-flop of the present invention, the logical amplitude V _lM of the output signal D _M of the master latch circuit 95 is the selector circuit 97.
Of the output signal D _{S of the} slave latch circuit 96 or the logical amplitude V _lS of the output signal D _L of the slave latch circuit 96, for example, 1/2 of those
Is set to the size of. This is each constant current source
If the current value of 60,61,62,63 is I ₁ and the resistance value of resistors 43,44,45 is R _S , the logical amplitude V _lS is shown by V _lS I ₁ · R _S , and the master latch circuit In 95, assuming that the resistance values of the resistors 40 and 41 are R _M , the logical amplitude V _lM of the output signal D _M is given by V _lM I ₁ · R _M The resistance values R _M and R _S may be set so as to satisfy the relationship. Further, in the master latch circuit 95, the resistor 42 is connected to the resistors 40, 4
It is connected between 1 and the first power supply potential 70. Resistance 42
Since a current of almost I ₁ always flows through this resistor,
_{If CQ} , the output signal D _M of the master latch circuit 95 is I ₁
The signal has a low DC level shifted by the potential difference of R _CQ . When this data is input to the slave latch circuit 96 when the output signal D _M of the master latch circuit 95 is high level, the collector coupling section 32 becomes low level, but in the present invention, the high level of D _M is Since it is shifted to the DC potential side lower than the conventional one, the collector potential of the transistor 7 does not become lower than the base potential until it is saturated, and as a result, the delay of the propagation delay time of the slave latch circuit is prevented. Therefore, the flip-flop can operate at high speed. Moreover, because of the logic amplitude V _lM 1/2 logic amplitude V _lS, high level, a direct current level to a low level in both approaches the first reference potential V _R1, reduction of margin for resulting noise and the reference potential fluctuation However, in the slave latch circuit 96, the first reference potential V _R1 is abolished, and the input transistor 7 is used instead.
It is possible to secure a margin and obtain stable high-speed operation by inputting D _M , which is the inverted signal of the data signal D _M input to. As described above, the present invention includes at least the first and second transistors, the first emitter coupling section in which the emitters of the first and second transistors are coupled to each other, and the third And a fourth transistor, a second emitter coupling part in which emitters of the third and fourth transistors are coupled to each other, a fifth transistor having a collector connected to the first emitter coupling part, and A sixth transistor having a collector connected to the second emitter coupling section, and having three emitter coupling sections of a third emitter coupling section in which the emitters of the fifth and sixth transistors are coupled to each other. A first collector coupling part in which the collector of the first transistor, the collector of the third transistor and the base of the fourth transistor are connected to each other , A collector of the second transistor, a collector of the fourth transistor, and a base of the third transistor are connected to each other, and have two collector coupling parts of a second collector coupling part. The second collector coupling section includes a common collector resistance section including first and second resistors each having one end connected to each other, and the other ends of the first and second resistances being coupled to each other. A first resistor having one end connected to the third emitter coupling part and one end connected to the third emitter coupling part.
Constant current source of the third resistor, the constant power source connected to the other end of the third resistor from the first power source potential to a second power source potential connected to the other end of the first constant current source A first latch circuit for flowing a current to perform a differential operation; and a seventh and an eighth transistor.
A fourth emitter coupling part in which the emitters of the transistors are coupled to each other, and a ninth and a tenth transistor,
A fifth emitter coupling section in which the emitters of the ninth and tenth transistors are coupled to each other, an eleventh transistor having a collector connected to the fourth emitter coupling section, and a collector in the fifth emitter coupling section. And a twelfth transistor connected to each other, wherein the emitters of the eleventh and twelfth transistors have three emitter coupling parts of a sixth emitter coupling part, and the collector of the seventh transistor And a third collector coupling part in which the collector of the ninth transistor and the base of the tenth transistor are connected to each other, the collector of the eighth transistor, the collector of the tenth transistor, and the ninth transistor Has two collector coupling parts, the bases of which are connected to each other, and the third and fourth collector coupling parts.
One end is connected to each collector coupling part of the other, and the other end has fourth and fifth resistors commonly connected to the first power supply potential, and one end is connected to the sixth emitter coupling part, A second latch circuit having a second constant current source whose other end is connected to the second power supply potential and having both positive logic output and negative logic output of the first latch circuit as balanced inputs; , A plurality of transistors whose emitters are coupled to each other and whose collectors are directly or via resistors connected to the first power supply potential, and a constant current source is coupled to the point where the emitters of the plurality of transistors are coupled to each other The gate circuit includes at least two gate circuits that perform a differential operation by flowing a constant current toward the second power supply potential, and select one of the inputs of the gate circuits to select the first circuit. The input to the latch circuit And a signal which is propagated from the first latch circuit to the second latch circuit and has a logical amplitude smaller than the logical amplitude of the input / output signal with the outside of the circuit and is shifted to a low DC level. Is generated because the collector potential of the input transistor of the second latch circuit that receives the output signal of the first latch circuit becomes too low when the signal input to the base is at high level. It is possible to prevent the saturated state of the transistor, and prevent the increase of the propagation delay time in the second latch circuit caused by the saturated state, thereby enabling the high-speed operation of the flip-flop. Further, in the second latch circuit, and waste the first reference voltage which has been used as a reference for the input data D _M, connects the inverted data D _M of the input data D _M Instead, the first latch 2nd by balance signal by positive logic output and negative logic output of circuit
The configuration in which the latch circuit is driven has an effect that a sufficient margin can be secured and stable high-speed operation can be performed.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing a configuration of a flip-flop according to an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a configuration example of a flip-flop according to the prior art. 1 to 19 ... Transistor, 40 to 46 ... Resistor, 60 to 63 ... Constant current source, 20 to 27 ... Emitter coupling section, 30 to 36 ... Collector coupling section, 5
0 ... Common collector resistance part, 70 ... First power supply potential, 71 ... Second
Power supply potential, 72 ... First reference potential, 73 ... Second reference potential, 80, 82 ... Input data signal terminal, 81, 83 ... Select signal terminal, 90 ... Clock signal terminal, 75 ... Data output terminal, 95 … Master latch circuit, 96… Slave latch circuit, 97… Selector circuit.

Claims (1)

(57) [Claims] A first emitter coupling part including at least first and second transistors, wherein the emitters of the first and second transistors are coupled to each other; and third and fourth transistors, the third and fourth transistors A second emitter coupling part in which the emitters of the transistors are coupled to each other;
A fifth transistor having a collector connected to the emitter coupling section of the second transistor and a sixth transistor having a collector connected to the second emitter coupling section, wherein the emitters of the fifth and sixth transistors are coupled to each other. A third collector of the first emitter, a collector of the first transistor, a collector of the third transistor and a base of the fourth transistor are connected to each other. A second portion, a collector of the second transistor, a collector of the fourth transistor, and a base of the third transistor are connected to each other.
Of collector connections of the first and second resistors having two collector connections of one end connected to the first and second collector connections respectively. Has a common collector resistor part whose other ends are connected to each other,
A third resistor having one end connected to the common collector resistor portion, a first constant current source having one end connected to the third emitter coupling portion, and the other end of the third resistor A first latch circuit for causing a constant current to flow from the first power supply potential connected to the second power supply potential to the second power supply potential connected to the other end of the first constant current source for differential operation; A seventh and an eighth transistor, a fourth emitter coupling part in which the emitters of the seventh and the eighth transistor are coupled to each other, and a ninth and a tenth transistor, and a ninth and a tenth transistor A fifth emitter-coupled portion whose emitters are coupled to each other, an eleventh transistor whose collector is connected to the fourth emitter-coupled portion, and a twelfth transistor whose collector is connected to the fifth emitter-coupled portion And the 11th and 12th 6th emitter coupling part in which the emitters of the transistors are coupled to each other
And a collector of the seventh transistor, a collector of the ninth transistor, and a collector of the ninth transistor.
A third collector coupling part in which the bases of the tenth transistor are connected to each other, and a fourth collector in which the collector of the eighth transistor, the collector of the tenth transistor and the base of the ninth transistor are connected to each other A fourth and a fifth collector coupling section having two collector coupling sections each having one end connected to each of the third and fourth collector coupling sections and the other end commonly connected to the first power supply potential. A resistor having one end connected to the sixth emitter coupling part,
A second latch circuit having a second constant current source whose other end is connected to the second power supply potential and having both positive logic output and negative logic output of the first latch circuit as balanced inputs; , A plurality of transistors whose emitters are coupled to each other and whose collectors are directly or via resistors connected to the first power supply potential, and a constant current source is coupled to a point where the emitters of the plurality of transistors are coupled to each other The gate circuit includes at least two gate circuits that perform a differential operation by flowing a constant current toward the second power supply potential, and select one of the inputs of the gate circuits to select the first circuit. And a selector circuit which is an input to the latch circuit, wherein only the propagation signal from the first latch circuit to the second latch circuit has a logical amplitude smaller than the logical amplitude of an input / output signal with the outside of the circuit and is low. Flip-flop, characterized in that to operate in the signal obtained by shifting the flow level.