JPS5720843A - High-speed subtracting circuit - Google Patents

High-speed subtracting circuit

Info

Publication number
JPS5720843A
JPS5720843A JP9604780A JP9604780A JPS5720843A JP S5720843 A JPS5720843 A JP S5720843A JP 9604780 A JP9604780 A JP 9604780A JP 9604780 A JP9604780 A JP 9604780A JP S5720843 A JPS5720843 A JP S5720843A
Authority
JP
Japan
Prior art keywords
output
subtracting circuit
comparator
denoted
speed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9604780A
Other languages
Japanese (ja)
Inventor
Hideyuki Tsujimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP9604780A priority Critical patent/JPS5720843A/en
Publication of JPS5720843A publication Critical patent/JPS5720843A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50Adding; Subtracting
    • G06F7/505Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804Details
    • G06F2207/3808Details concerning the type of numbers or the way they are handled
    • G06F2207/3832Less usual number representations
    • G06F2207/3836One's complement

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)

Abstract

PURPOSE:To realize a high-speed subtraction with just a pass through an adding circuit, by using a comparator for a subtracting process of two numbers showing the binary numbers. CONSTITUTION:A binary number A comprising A0, A1-AN is compared with a binary number B comprising B0, B1-BN. In this case, the output of a comparator is set at level ''0'' and ''1'' with A<B and A>B, respectively. In the case of A>B, a carry input CIN is at ''1'', and accordingly, the output S of an adding circuit is denoted by S=A+B'+1. Since the output of an inverter INV is at ''0'', the subtraction value D is denoted by D=S. Then the output S goes to S=A+B' because the input CIN is at ''0'' in A<B. At the same time, D=S' is satisfied since the output of the INV is at ''1''.
JP9604780A 1980-07-14 1980-07-14 High-speed subtracting circuit Pending JPS5720843A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9604780A JPS5720843A (en) 1980-07-14 1980-07-14 High-speed subtracting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9604780A JPS5720843A (en) 1980-07-14 1980-07-14 High-speed subtracting circuit

Publications (1)

Publication Number Publication Date
JPS5720843A true JPS5720843A (en) 1982-02-03

Family

ID=14154550

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9604780A Pending JPS5720843A (en) 1980-07-14 1980-07-14 High-speed subtracting circuit

Country Status (1)

Country Link
JP (1) JPS5720843A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61155219A (en) * 1984-12-27 1986-07-14 Babcock Hitachi Kk Oxidizing method of calcium sulfite
JPH0465893U (en) * 1990-10-17 1992-06-09

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61155219A (en) * 1984-12-27 1986-07-14 Babcock Hitachi Kk Oxidizing method of calcium sulfite
JPH0469089B2 (en) * 1984-12-27 1992-11-05 Babcock Hitachi Kk
JPH0465893U (en) * 1990-10-17 1992-06-09

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