JPS5686536A - Preset circuit for electronic counter - Google Patents
Preset circuit for electronic counterInfo
- Publication number
- JPS5686536A JPS5686536A JP16441679A JP16441679A JPS5686536A JP S5686536 A JPS5686536 A JP S5686536A JP 16441679 A JP16441679 A JP 16441679A JP 16441679 A JP16441679 A JP 16441679A JP S5686536 A JPS5686536 A JP S5686536A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- pulse train
- counter
- input
- delivered
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
- H03K23/66—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses
- H03K23/662—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses by adding or suppressing pulses
Landscapes
- Electric Clocks (AREA)
- Electronic Switches (AREA)
Abstract
PURPOSE:To enable preset operation at one section, by the addition or subtraction of the counter with one preset switch only. CONSTITUTION:The output of a monostable multivibrator 4 is delivered to an inverter 5. The output of the inverter 5 and that of a pulse train generating circuit 8 are respectively input to two input terminals of the AND gate circuit 6. During the operation of the multivibrator 4, the circuit 6 is closed and the pulse train produced from the pulse train generating circuit 8 is not delivered to the next stage, and when the multivibrator 4 is finished for the operation, then the circuit 6 is set and the pulse train is delivered to the next stage. The output from the circuit 6 is input to the UP-terminal of the counter 7 and the counter performs addition one by one every time when one pulse of the pulse train is input. This addition is kept while the preset switch 1 is depressed.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16441679A JPS5686536A (en) | 1979-12-17 | 1979-12-17 | Preset circuit for electronic counter |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16441679A JPS5686536A (en) | 1979-12-17 | 1979-12-17 | Preset circuit for electronic counter |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5686536A true JPS5686536A (en) | 1981-07-14 |
JPS6214131B2 JPS6214131B2 (en) | 1987-03-31 |
Family
ID=15792724
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16441679A Granted JPS5686536A (en) | 1979-12-17 | 1979-12-17 | Preset circuit for electronic counter |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5686536A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6123729U (en) * | 1984-07-16 | 1986-02-12 | 富士通テン株式会社 | Communication device input device |
-
1979
- 1979-12-17 JP JP16441679A patent/JPS5686536A/en active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6123729U (en) * | 1984-07-16 | 1986-02-12 | 富士通テン株式会社 | Communication device input device |
Also Published As
Publication number | Publication date |
---|---|
JPS6214131B2 (en) | 1987-03-31 |
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