JPS5687929A - Switch circuit - Google Patents
Switch circuitInfo
- Publication number
- JPS5687929A JPS5687929A JP16518079A JP16518079A JPS5687929A JP S5687929 A JPS5687929 A JP S5687929A JP 16518079 A JP16518079 A JP 16518079A JP 16518079 A JP16518079 A JP 16518079A JP S5687929 A JPS5687929 A JP S5687929A
- Authority
- JP
- Japan
- Prior art keywords
- input
- switch
- output
- low
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
- H01H9/00—Details of switching devices, not covered by groups H01H1/00 - H01H7/00
- H01H9/54—Circuit arrangements not adapted to a particular application of the switching device and for which no provision exists elsewhere
Landscapes
- Input From Keyboards Or The Like (AREA)
- Electronic Switches (AREA)
Abstract
PURPOSE:To make effective the switch finally depressed only, by inhibiting the input of other switches, when closing one switch. CONSTITUTION:When the switch Sd in a circuit 3-2 is closed, the input of an inverter 4 and an AND gate 5 is low. Since the output of the inverter 4 is high, the output of an NAND gate 6 is energized low. At this time point, since the output of an NOR gate 7 is energized high, a monostable multivibrator 8 is triggered and a positive pulse is fed to a clock input T of a flip-flop 9 to set the flip-flop 9 of the circuit 3-2. In this case, since a low input is present at the data input D, the output of the flip-flop 9 is low. By depressing the switch Sd, the input inhibiting signal is fed to the lower rank NAND gate 6 and NOR gate 7 from the upper rank.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16518079A JPS5687929A (en) | 1979-12-18 | 1979-12-18 | Switch circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16518079A JPS5687929A (en) | 1979-12-18 | 1979-12-18 | Switch circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5687929A true JPS5687929A (en) | 1981-07-17 |
Family
ID=15807360
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16518079A Pending JPS5687929A (en) | 1979-12-18 | 1979-12-18 | Switch circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5687929A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58187027A (en) * | 1982-04-27 | 1983-11-01 | Nec Corp | Signal switching circuit |
JP2013185784A (en) * | 2012-03-09 | 2013-09-19 | Aisin Seiki Co Ltd | Cogeneration system |
-
1979
- 1979-12-18 JP JP16518079A patent/JPS5687929A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58187027A (en) * | 1982-04-27 | 1983-11-01 | Nec Corp | Signal switching circuit |
JP2013185784A (en) * | 2012-03-09 | 2013-09-19 | Aisin Seiki Co Ltd | Cogeneration system |
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