JPS5547739A - Input circuit - Google Patents
Input circuitInfo
- Publication number
- JPS5547739A JPS5547739A JP12072978A JP12072978A JPS5547739A JP S5547739 A JPS5547739 A JP S5547739A JP 12072978 A JP12072978 A JP 12072978A JP 12072978 A JP12072978 A JP 12072978A JP S5547739 A JPS5547739 A JP S5547739A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- priority
- output
- row
- column
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
- H03J5/00—Discontinuous tuning; Selecting predetermined frequencies; Selecting frequency bands with or without continuous tuning in one or more of the bands, e.g. push-button tuning, turret tuner
- H03J5/02—Discontinuous tuning; Selecting predetermined frequencies; Selecting frequency bands with or without continuous tuning in one or more of the bands, e.g. push-button tuning, turret tuner with variable tuning element having a number of predetermined settings and adjustable to a desired one of these settings
Abstract
PURPOSE:To enable to select one key switch according to the priority even if two or more key switches are depressed at the same time, by providing the priority circuit having a given regularity. CONSTITUTION:The clock pulse in time sharing is fed to the row output terminal of the keyboard 11 from the common signal generation circuit 12, the output signal from the clumn output terminal is detected at the detection circuit 14 to open the first gate circuit 13, clock pulse is fetched to the row latch circuit 16, and output is made from the row priority circuit 17 according to a given priority. On the other hand, the second gate circuit 15 is opened with the control signal generation circuit 20, the output signal from the clumn output terminal is fetched to the column latch circuit 18, and output is made from the column priority circuit 19 according to a given priority. Further, the output signal from the row and column priority circuits 17 and 18 is fed to the control circuit 22 to select the number of key switch.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12072978A JPS5547739A (en) | 1978-09-30 | 1978-09-30 | Input circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12072978A JPS5547739A (en) | 1978-09-30 | 1978-09-30 | Input circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5547739A true JPS5547739A (en) | 1980-04-04 |
Family
ID=14793541
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12072978A Pending JPS5547739A (en) | 1978-09-30 | 1978-09-30 | Input circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5547739A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57176447A (en) * | 1981-04-24 | 1982-10-29 | Fujitsu Ltd | A plurality word instantaneous input type digital input circuit system |
WO1984002594A1 (en) * | 1982-12-24 | 1984-07-05 | Fanuc Ltd | System for preventing erroneous key operation |
US4680572A (en) * | 1981-12-14 | 1987-07-14 | Ncr Corporation | Chord entry keying of data fields |
-
1978
- 1978-09-30 JP JP12072978A patent/JPS5547739A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57176447A (en) * | 1981-04-24 | 1982-10-29 | Fujitsu Ltd | A plurality word instantaneous input type digital input circuit system |
JPS636896B2 (en) * | 1981-04-24 | 1988-02-12 | Fujitsu Ltd | |
US4680572A (en) * | 1981-12-14 | 1987-07-14 | Ncr Corporation | Chord entry keying of data fields |
WO1984002594A1 (en) * | 1982-12-24 | 1984-07-05 | Fanuc Ltd | System for preventing erroneous key operation |
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