JPS55134455A - Parity forming circuit - Google Patents

Parity forming circuit

Info

Publication number
JPS55134455A
JPS55134455A JP4072179A JP4072179A JPS55134455A JP S55134455 A JPS55134455 A JP S55134455A JP 4072179 A JP4072179 A JP 4072179A JP 4072179 A JP4072179 A JP 4072179A JP S55134455 A JPS55134455 A JP S55134455A
Authority
JP
Japan
Prior art keywords
circuit
data
bit
output
parity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4072179A
Other languages
Japanese (ja)
Other versions
JPS6041772B2 (en
Inventor
Fumio Hoshi
Teruyoshi Mita
Masao Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP54040721A priority Critical patent/JPS6041772B2/en
Publication of JPS55134455A publication Critical patent/JPS55134455A/en
Publication of JPS6041772B2 publication Critical patent/JPS6041772B2/en
Expired legal-status Critical Current

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  • Detection And Correction Of Errors (AREA)

Abstract

PURPOSE: To give a very simple constitution to a circuit by constituting the circuit so that a new parity bit can be obtained by the parity bit of a data processing circuit and data of a part of it.
CONSTITUTION: Data group A is output from data processing circuit 1. Data a2 of this data group A is processed into data a3 by data processing circuit 3. Accompanied with this processing, new parity bit p2 is formed according to data a2 and parity bit p1 by parity forming circuit 7. In circuit 7, data a2 is transferred to exclusive OR circuit E1 for every bit, and bit P1 is transferred to exclusive OR circuit E2, and the output of circuit E1 is transferred to the other input of circuit E2. Consequently, since data a2 is 10 and bit P1 is 1 now, logic 1 is output from circuit E1, and logic 0 is output from circuit E2, and bit P2 becomes logic 0. Thus, parity bit P2 can be obtained with a very simple circuit.
COPYRIGHT: (C)1980,JPO&Japio
JP54040721A 1979-04-04 1979-04-04 Parity creation circuit Expired JPS6041772B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54040721A JPS6041772B2 (en) 1979-04-04 1979-04-04 Parity creation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54040721A JPS6041772B2 (en) 1979-04-04 1979-04-04 Parity creation circuit

Publications (2)

Publication Number Publication Date
JPS55134455A true JPS55134455A (en) 1980-10-20
JPS6041772B2 JPS6041772B2 (en) 1985-09-18

Family

ID=12588455

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54040721A Expired JPS6041772B2 (en) 1979-04-04 1979-04-04 Parity creation circuit

Country Status (1)

Country Link
JP (1) JPS6041772B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6280163U (en) * 1985-11-08 1987-05-22
JPH0247382Y2 (en) * 1986-06-30 1990-12-13

Also Published As

Publication number Publication date
JPS6041772B2 (en) 1985-09-18

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