JPS5331927A - Logical sum circuit - Google Patents

Logical sum circuit

Info

Publication number
JPS5331927A
JPS5331927A JP10650876A JP10650876A JPS5331927A JP S5331927 A JPS5331927 A JP S5331927A JP 10650876 A JP10650876 A JP 10650876A JP 10650876 A JP10650876 A JP 10650876A JP S5331927 A JPS5331927 A JP S5331927A
Authority
JP
Japan
Prior art keywords
logical sum
sum circuit
teh
small number
conventional case
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10650876A
Other languages
Japanese (ja)
Inventor
Ryota Kasai
Tadakatsu Kimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP10650876A priority Critical patent/JPS5331927A/en
Publication of JPS5331927A publication Critical patent/JPS5331927A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To obtain a new full adder circuit which can obtain a high response velocity using MIS transistors in a considerably small number compared with teh conventional case.
COPYRIGHT: (C)1978,JPO&Japio
JP10650876A 1976-09-06 1976-09-06 Logical sum circuit Pending JPS5331927A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10650876A JPS5331927A (en) 1976-09-06 1976-09-06 Logical sum circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10650876A JPS5331927A (en) 1976-09-06 1976-09-06 Logical sum circuit

Publications (1)

Publication Number Publication Date
JPS5331927A true JPS5331927A (en) 1978-03-25

Family

ID=14435357

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10650876A Pending JPS5331927A (en) 1976-09-06 1976-09-06 Logical sum circuit

Country Status (1)

Country Link
JP (1) JPS5331927A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58211252A (en) * 1982-06-03 1983-12-08 Toshiba Corp Total adder
JPS59201527A (en) * 1983-04-15 1984-11-15 アイテイ−テイ−・インダストリ−ズ・インコ−ポレ−テツド Exclusive or or exclusive nor gate
JPS60247733A (en) * 1984-05-24 1985-12-07 Toshiba Corp Logical arithmetic circuit
JPS6143005U (en) * 1984-08-21 1986-03-20 松野株式会社 wooden bent plywood
JPH04147803A (en) * 1990-10-11 1992-05-21 Hyogo Izumi Manufacture of curved laminated lumber

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3767906A (en) * 1972-01-21 1973-10-23 Rca Corp Multifunction full adder

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3767906A (en) * 1972-01-21 1973-10-23 Rca Corp Multifunction full adder

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58211252A (en) * 1982-06-03 1983-12-08 Toshiba Corp Total adder
JPS59201527A (en) * 1983-04-15 1984-11-15 アイテイ−テイ−・インダストリ−ズ・インコ−ポレ−テツド Exclusive or or exclusive nor gate
JPH0552529B2 (en) * 1983-04-15 1993-08-05 Itt
JPS60247733A (en) * 1984-05-24 1985-12-07 Toshiba Corp Logical arithmetic circuit
JPS6143005U (en) * 1984-08-21 1986-03-20 松野株式会社 wooden bent plywood
JPH04147803A (en) * 1990-10-11 1992-05-21 Hyogo Izumi Manufacture of curved laminated lumber

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