JPS55123238A - Power supply system of logic circuit - Google Patents

Abstract

PURPOSE:To reduce power consumption by providing a logic circuit, controlled synchronizing with a clock signal, with a current supply path extending to the logic circuit only during fixed periods before and after either the rise or fall point of the clock signal including it. CONSTITUTION:Current supply control circuit 2 is provided which supplies a current to NAND element 1 of a synchronous logic circuit with a clock signal. Here, terminals (a) and (b) are input signal terminals, and terminal (c) an output signal terminal. When control pulse P4 of the same cycle as clock signal CLK and advancing in phase is applied to control terminal (d) of circuit 2, only pulse P4 of level ''H'' turns transistor Q1 ON to consume power. Input signals P1 and P2 are changed at the rise point of signal CLK and output signal P3' from terminal (c) are also changed in level by pulse P4, but inputted to the poststage sequence circuit at rise points A, B, C, and D of signal CLK, so that the power consumption will be reduced without exerting any influence on logic operation.