JPS55100747A - Operating-power reduction control system - Google Patents

Operating-power reduction control system

Info

Publication number
JPS55100747A
JPS55100747A JP850579A JP850579A JPS55100747A JP S55100747 A JPS55100747 A JP S55100747A JP 850579 A JP850579 A JP 850579A JP 850579 A JP850579 A JP 850579A JP S55100747 A JPS55100747 A JP S55100747A
Authority
JP
Japan
Prior art keywords
circuit
timing
timing signal
stand
clocks
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP850579A
Other languages
Japanese (ja)
Inventor
Kensaku Wada
Koichi Fujita
Masaharu Kimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP850579A priority Critical patent/JPS55100747A/en
Publication of JPS55100747A publication Critical patent/JPS55100747A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption

Abstract

PURPOSE:To reduce the power consumption of a circuit part by increasing the dividing ratio of clocks applied to a timing generating circuit while lowering the frequency of a timing signal applied to the circuit part by dringing a divider circuit under the control of a stand-by operation circuit. CONSTITUTION:Synchronizing with clocks from clock generating circuit 2, timing generating circuit 4 generates a timing signal and a circuit part is provided which operates at the timing according to the timing signal from circuit 4. Here, divider circuit 3 is provided between circuits 2 and 4 and stand-by operation circuit 5 exercises control over circuit 3 to increase the dividing ratio of clocks applied to circuit 4 in stand-by operation mode while lowering the frequency of the timing signal applied to the circuit part. Consequently, the power consumption of the circuit part can be reduced.
JP850579A 1979-01-27 1979-01-27 Operating-power reduction control system Pending JPS55100747A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP850579A JPS55100747A (en) 1979-01-27 1979-01-27 Operating-power reduction control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP850579A JPS55100747A (en) 1979-01-27 1979-01-27 Operating-power reduction control system

Publications (1)

Publication Number Publication Date
JPS55100747A true JPS55100747A (en) 1980-07-31

Family

ID=11694970

Family Applications (1)

Application Number Title Priority Date Filing Date
JP850579A Pending JPS55100747A (en) 1979-01-27 1979-01-27 Operating-power reduction control system

Country Status (1)

Country Link
JP (1) JPS55100747A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0223760A (en) * 1988-07-13 1990-01-25 Toshiba Corp Telephone system
US5548765A (en) * 1990-08-28 1996-08-20 Seiko Epson Corporation Power saving display subsystem for portable computers

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0223760A (en) * 1988-07-13 1990-01-25 Toshiba Corp Telephone system
US5548765A (en) * 1990-08-28 1996-08-20 Seiko Epson Corporation Power saving display subsystem for portable computers

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