JPS6416022A - Bus driving circuit - Google Patents

Bus driving circuit

Info

Publication number
JPS6416022A
JPS6416022A JP62169679A JP16967987A JPS6416022A JP S6416022 A JPS6416022 A JP S6416022A JP 62169679 A JP62169679 A JP 62169679A JP 16967987 A JP16967987 A JP 16967987A JP S6416022 A JPS6416022 A JP S6416022A
Authority
JP
Japan
Prior art keywords
potential
bus
output
power supply
delay time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62169679A
Other languages
Japanese (ja)
Inventor
Seiichi Saito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62169679A priority Critical patent/JPS6416022A/en
Publication of JPS6416022A publication Critical patent/JPS6416022A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent the flow of power supply current to the CMOS input stage of a receiver by bringing quickly a potential of a bus to the potential of a power supply connected via a pull-up resistor when the bus reaches a high impedance state. CONSTITUTION:An output control circuit 7 controls the output of an output stage circuit 4 to be a 1st potential in response to the change in an output control signal C, then receiving a timing signal T from a delay time generating circuit 6, the output of the output stage circuit 4 is brought into a high impedance state after a delay time sufficiently to charge the bus 1 to the 1st potential. The bus 1 is charged to the 1st potential equal to the potential of the power supply 2 connected via a pull-up resistor 3 while the above mentioned delay time. Thus, the potential of the bus does not stay in the intermediate potential state when the bus is brought into a high impedance state. Thus, the increase in the power consumption due to the power supply current flowing to the CMOS output stage of the receiver is prevented.
JP62169679A 1987-07-09 1987-07-09 Bus driving circuit Pending JPS6416022A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62169679A JPS6416022A (en) 1987-07-09 1987-07-09 Bus driving circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62169679A JPS6416022A (en) 1987-07-09 1987-07-09 Bus driving circuit

Publications (1)

Publication Number Publication Date
JPS6416022A true JPS6416022A (en) 1989-01-19

Family

ID=15890898

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62169679A Pending JPS6416022A (en) 1987-07-09 1987-07-09 Bus driving circuit

Country Status (1)

Country Link
JP (1) JPS6416022A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04150224A (en) * 1990-10-15 1992-05-22 Internatl Business Mach Corp <Ibm> Integrated circuit
CN108303033A (en) * 2018-01-17 2018-07-20 厦门大学 The monitoring device and monitoring method of the spacing of Slanted ejecting mechanism of injection mould and guide pad

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04150224A (en) * 1990-10-15 1992-05-22 Internatl Business Mach Corp <Ibm> Integrated circuit
CN108303033A (en) * 2018-01-17 2018-07-20 厦门大学 The monitoring device and monitoring method of the spacing of Slanted ejecting mechanism of injection mould and guide pad

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