JPS5730189A - Ic memory device - Google Patents

Ic memory device

Info

Publication number
JPS5730189A
JPS5730189A JP10373980A JP10373980A JPS5730189A JP S5730189 A JPS5730189 A JP S5730189A JP 10373980 A JP10373980 A JP 10373980A JP 10373980 A JP10373980 A JP 10373980A JP S5730189 A JPS5730189 A JP S5730189A
Authority
JP
Japan
Prior art keywords
power source
turns
line
power line
device power
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10373980A
Other languages
Japanese (ja)
Inventor
Osamu Yamamoto
Tsukasa Igarashi
Tsuneo Baba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP10373980A priority Critical patent/JPS5730189A/en
Publication of JPS5730189A publication Critical patent/JPS5730189A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/141—Battery and back-up supplies

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To extend the time when data can be held, by suppressing a backup power source current when a device power source is turned off and on. CONSTITUTION:The power line (a) of an IC memory array 1 of CMOS structure is connected to a device power source 13 and a backup power source 14 through diode DIs 15 and 16. Normally, the DI15 turns on to supply the output voltage V1 of the device power source 13 to the power line (a). If the device power source 13 is turned off, the DI16 turns on to supply the output voltage V2 (V1>V2) of the backup power source 14 to the power line. At this time, the DI15 turns off to disconnect the device power source 13 from the power line (a). The signal input line (b) of the IC memory array 1 is connected to the power line (a) via a pull-up resistance 13.
JP10373980A 1980-07-30 1980-07-30 Ic memory device Pending JPS5730189A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10373980A JPS5730189A (en) 1980-07-30 1980-07-30 Ic memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10373980A JPS5730189A (en) 1980-07-30 1980-07-30 Ic memory device

Publications (1)

Publication Number Publication Date
JPS5730189A true JPS5730189A (en) 1982-02-18

Family

ID=14361983

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10373980A Pending JPS5730189A (en) 1980-07-30 1980-07-30 Ic memory device

Country Status (1)

Country Link
JP (1) JPS5730189A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61278097A (en) * 1985-06-03 1986-12-08 Nippon Telegr & Teleph Corp <Ntt> Memory integrated circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61278097A (en) * 1985-06-03 1986-12-08 Nippon Telegr & Teleph Corp <Ntt> Memory integrated circuit

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