JPS5710531A - Level conversion circuit - Google Patents
Level conversion circuitInfo
- Publication number
- JPS5710531A JPS5710531A JP8382280A JP8382280A JPS5710531A JP S5710531 A JPS5710531 A JP S5710531A JP 8382280 A JP8382280 A JP 8382280A JP 8382280 A JP8382280 A JP 8382280A JP S5710531 A JPS5710531 A JP S5710531A
- Authority
- JP
- Japan
- Prior art keywords
- level
- microcomputer
- resistance
- conversion circuit
- peripheral
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4072—Drivers or receivers
Abstract
PURPOSE:To simplify the circuit, by a parallel connection of a diode and a resistance between a signal line and a power supply of a microcomputer and its peripheral device. CONSTITUTION:When data are written in from a microcomputer 11 to a peripheral IC12 at a relation of the power supply voltage VDD>VCC, a switch SWW is turned on. When the microcomputer 11 outputs at ''0'' level, the level of a line 13 is kept to ''0'' level through a resistance R, and when ''1'' level is outputted, the level is clamped to the VCC through a diode D. When the microcomputer 11 reads in data from the peripheral IC12, the switch SWR is turned ON. When the IC12 outputs ''1'' level, the level of the line 13 is increased to the VDD through the resistance R.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8382280A JPS5710531A (en) | 1980-06-20 | 1980-06-20 | Level conversion circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8382280A JPS5710531A (en) | 1980-06-20 | 1980-06-20 | Level conversion circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5710531A true JPS5710531A (en) | 1982-01-20 |
Family
ID=13813376
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8382280A Pending JPS5710531A (en) | 1980-06-20 | 1980-06-20 | Level conversion circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5710531A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5958859A (en) * | 1982-09-29 | 1984-04-04 | Hitachi Ltd | Semiconductor integrated circuit |
JPH06129095A (en) * | 1992-09-25 | 1994-05-10 | Toda Constr Co Ltd | Mat for curing concrete |
CN101895219A (en) * | 2010-07-22 | 2010-11-24 | 鞍山起重控制设备有限公司 | Pulse trigger type master control signal level converter and application method thereof |
-
1980
- 1980-06-20 JP JP8382280A patent/JPS5710531A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5958859A (en) * | 1982-09-29 | 1984-04-04 | Hitachi Ltd | Semiconductor integrated circuit |
JPH06129095A (en) * | 1992-09-25 | 1994-05-10 | Toda Constr Co Ltd | Mat for curing concrete |
CN101895219A (en) * | 2010-07-22 | 2010-11-24 | 鞍山起重控制设备有限公司 | Pulse trigger type master control signal level converter and application method thereof |
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