JPS5469040A - Driving system for c-mos circuit - Google Patents

Driving system for c-mos circuit

Info

Publication number
JPS5469040A
JPS5469040A JP13601777A JP13601777A JPS5469040A JP S5469040 A JPS5469040 A JP S5469040A JP 13601777 A JP13601777 A JP 13601777A JP 13601777 A JP13601777 A JP 13601777A JP S5469040 A JPS5469040 A JP S5469040A
Authority
JP
Japan
Prior art keywords
phi
level
mos
ratioless
under
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13601777A
Other languages
Japanese (ja)
Inventor
Shinichi Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP13601777A priority Critical patent/JPS5469040A/en
Publication of JPS5469040A publication Critical patent/JPS5469040A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals
    • H03K19/0963—Synchronous circuits, i.e. using clock signals using transistors of complementary type

Abstract

PURPOSE:To realize further reduction of the power consumption for the ratioless circuit comprising C-MOS by controlling the level of the clock signal under the non- active state so that the ratioless part may be put under the precharge state. CONSTITUTION:In the non-active state under which the action stip comand is given to the C-MOS ratioless circuit, clock signal phi of ''H'' is applied to the gate of N- channel MOS.T1. Thus, T1 is turned on and input point A of inverter I0 is held nearly at power voltage VDD as long as phi is at ''H'' and regardless of input signal IN of ratioless part R, and I0 leads out the output steadily to output terminal OUT without reaching the transit region. By the fact that point A is held at VDD, the precharge period is secured for R without being affected by the level of signal IN. Al so, the level of phi is decided by the type of MOS constituting R, and the level of phi is controlled to ''H'' and ''L'' in order to secure the precharge period of R.
JP13601777A 1977-11-11 1977-11-11 Driving system for c-mos circuit Pending JPS5469040A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13601777A JPS5469040A (en) 1977-11-11 1977-11-11 Driving system for c-mos circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13601777A JPS5469040A (en) 1977-11-11 1977-11-11 Driving system for c-mos circuit

Publications (1)

Publication Number Publication Date
JPS5469040A true JPS5469040A (en) 1979-06-02

Family

ID=15165229

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13601777A Pending JPS5469040A (en) 1977-11-11 1977-11-11 Driving system for c-mos circuit

Country Status (1)

Country Link
JP (1) JPS5469040A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4659948A (en) * 1983-07-15 1987-04-21 Northern Telecom Limited Programmable logic array
JPH01260924A (en) * 1988-04-11 1989-10-18 Fujitsu Ltd Pla control system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4659948A (en) * 1983-07-15 1987-04-21 Northern Telecom Limited Programmable logic array
JPH01260924A (en) * 1988-04-11 1989-10-18 Fujitsu Ltd Pla control system

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