JPS57119523A - Programmable logic array - Google Patents

Programmable logic array

Info

Publication number
JPS57119523A
JPS57119523A JP56006994A JP699481A JPS57119523A JP S57119523 A JPS57119523 A JP S57119523A JP 56006994 A JP56006994 A JP 56006994A JP 699481 A JP699481 A JP 699481A JP S57119523 A JPS57119523 A JP S57119523A
Authority
JP
Japan
Prior art keywords
output
signal
array
programmable logic
enabled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56006994A
Other languages
Japanese (ja)
Inventor
Shigeru Maki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56006994A priority Critical patent/JPS57119523A/en
Publication of JPS57119523A publication Critical patent/JPS57119523A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
    • H03K19/17716—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register
    • H03K19/1772—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register with synchronous operation of at least one of the logical matrixes

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To shorten signal transfer time by simplifying a circuit, by putting an optional output line in an enabled state in accordance with the combination of inputs. CONSTITUTION:An OR array 4 is so constituted that an output controlling signal is outputted in correspondence to a signal for output, and an output controlling buffer 5 is provided with a gate circuit which opens by either of an external output enabling signal and the output control signal. Consequently, all output signals are put in enabled states by the external output enabling signal and the signal for output which corresponds to the output controlling signal of the OR array and is outputted in accordance with the combination of inputs to a programmable logic array is enabled.
JP56006994A 1981-01-19 1981-01-19 Programmable logic array Pending JPS57119523A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56006994A JPS57119523A (en) 1981-01-19 1981-01-19 Programmable logic array

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56006994A JPS57119523A (en) 1981-01-19 1981-01-19 Programmable logic array

Publications (1)

Publication Number Publication Date
JPS57119523A true JPS57119523A (en) 1982-07-26

Family

ID=11653679

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56006994A Pending JPS57119523A (en) 1981-01-19 1981-01-19 Programmable logic array

Country Status (1)

Country Link
JP (1) JPS57119523A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6292519A (en) * 1985-10-17 1987-04-28 Ricoh Co Ltd Programmable logic device provided with test circuit
US5027315A (en) * 1984-09-28 1991-06-25 Advanced Micro Devices, Inc. Programmable logic array using internally generated dynamic logic signals as selection signals for controlling its functions

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5027315A (en) * 1984-09-28 1991-06-25 Advanced Micro Devices, Inc. Programmable logic array using internally generated dynamic logic signals as selection signals for controlling its functions
JPS6292519A (en) * 1985-10-17 1987-04-28 Ricoh Co Ltd Programmable logic device provided with test circuit

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