JPS5610753A - Buffer control system - Google Patents
Buffer control systemInfo
- Publication number
- JPS5610753A JPS5610753A JP8504879A JP8504879A JPS5610753A JP S5610753 A JPS5610753 A JP S5610753A JP 8504879 A JP8504879 A JP 8504879A JP 8504879 A JP8504879 A JP 8504879A JP S5610753 A JPS5610753 A JP S5610753A
- Authority
- JP
- Japan
- Prior art keywords
- buffer
- data
- buffers
- under
- state
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
- H04J3/0626—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Time-Division Multiplex Systems (AREA)
Abstract
PURPOSE:To prevent both the underflow and the overflow by setting some of plural numbers of monitor buffers under the data full state and then setting other monitor buffers under the data vacant state each, thus ensuring the proper control for the buffer. CONSTITUTION:Data buffers 311 and 312 are set under the data vacant state; while data buffers 313 and 314 are set under the data full state respectively. And the memory state is monitored for each of buffers 311-314 by data buffers 321-324. Then transmitting data signal SD1 is written into buffer 311 with the fall of transmitting timing signal ST1, and at the same time buffer 321 is set under the data full state by the output of fall detecting circuit 33. Then the contents of buffer 311 is transferred to buffer 312 by clock CLK and via gates G1 and G4 owing to the fact that buffer 322 is under the data vacant state. Thus buffer 322 is set under the data vacant state. But the contents of buffer 312 is maintained there since buffer 313 is under the data full state. As a result, both the underflow and the overflow can be prevented, thus ensuring the proper control of the buffer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8504879A JPS5851458B2 (en) | 1979-07-06 | 1979-07-06 | Buffer control method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8504879A JPS5851458B2 (en) | 1979-07-06 | 1979-07-06 | Buffer control method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5610753A true JPS5610753A (en) | 1981-02-03 |
| JPS5851458B2 JPS5851458B2 (en) | 1983-11-16 |
Family
ID=13847781
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8504879A Expired JPS5851458B2 (en) | 1979-07-06 | 1979-07-06 | Buffer control method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5851458B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6033628A (en) * | 1983-08-04 | 1985-02-21 | Nec Corp | Variable queue memory |
| EP0188111A2 (en) * | 1984-12-18 | 1986-07-23 | Advanced Micro Devices, Inc. | Data stream synchronisers |
| JPS6252633A (en) * | 1985-09-02 | 1987-03-07 | Hitachi Ltd | Data transfer method |
-
1979
- 1979-07-06 JP JP8504879A patent/JPS5851458B2/en not_active Expired
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6033628A (en) * | 1983-08-04 | 1985-02-21 | Nec Corp | Variable queue memory |
| EP0188111A2 (en) * | 1984-12-18 | 1986-07-23 | Advanced Micro Devices, Inc. | Data stream synchronisers |
| JPS6252633A (en) * | 1985-09-02 | 1987-03-07 | Hitachi Ltd | Data transfer method |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5851458B2 (en) | 1983-11-16 |
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