JPS6480184A - Clock switching circuit - Google Patents

Abstract

PURPOSE:To prevent the occurrence of a fault such as deviated timing of system at changeover by sampling a selection signal by the 1st sampling means and an output signal of the sampling means by the 2nd sampling means respectively and controlling a gate means with respect to a clock pulse by the logic of the output signal of both the sampling means. CONSTITUTION:When a standard NTSC signal is inputted and a selection signal SE changes from H to L, an inverted output signal of a FF 40 and an output signal of a FF 42 change sequentially to H in the 1st clock changeover section, an output signal of a NOR gate 44 goes to an L to interrupt a clock pulse fSH. The output signal of the FFs 50, 52 changes sequentially to L in the 2nd clock changeover section, an output signal of a NOR gate 54 goes to H and a clock pulse fSC is outputted through an AND gate 56 and an OR gate 60. Thus, the 1st clock pulse is cancelled and outputted from the next clock pulse, then no fault place in the picture signal because the timing of write/readout is deviated.