JPS5769433A - Clock signal controlling system - Google Patents

Abstract

PURPOSE:To prevent the occurrence of an error between a clock and a half-cycle clock signal by generating the half-cycle clock by using one synchronizing signal for a normal clock or two synchronizing signals for a manual clock. CONSTITUTION:For a normal clock, a ''1'' is supplied from a switching terminal X to an AND/NAND gate 10. A clock signal (a) inputted from an input terminal A is delayed by a half cycle through an AND gate 11, an NOR gate 13, AND gates 8 and 9 of a delay circuit 7, and an AND gate 5 to be inputted to an NOR gate 6. Then, it is NORed with a signal passed through an AND gate 4 to obtain a half- cycle clock at an output terminal C. For a manual clock, on the other hand, a ''0'' is supplied to the switching terminal X to close and open the AND gates 11 and 12 respectively, and the clock signals (a) and (b) are inputted by turns from input terminals A and B in every manual operation.