JPS56145412A - Interruption signal receiving circuit - Google Patents

Interruption signal receiving circuit

Info

Publication number
JPS56145412A
JPS56145412A JP4797080A JP4797080A JPS56145412A JP S56145412 A JPS56145412 A JP S56145412A JP 4797080 A JP4797080 A JP 4797080A JP 4797080 A JP4797080 A JP 4797080A JP S56145412 A JPS56145412 A JP S56145412A
Authority
JP
Japan
Prior art keywords
interruption
signal
receiving circuit
time
oscillator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4797080A
Other languages
Japanese (ja)
Other versions
JPS6217778B2 (en
Inventor
Shinya Sekine
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP4797080A priority Critical patent/JPS56145412A/en
Publication of JPS56145412A publication Critical patent/JPS56145412A/en
Publication of JPS6217778B2 publication Critical patent/JPS6217778B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt

Abstract

PURPOSE:To transfer an interruption signal securely by providing an oscillating circuit, oscillating to generate a signal at constant intervals of time, between an extended interruption receiving circut and an interruption receiving circuit, and by using the output of AND between the transmitted output signal and an interruption signal as an interruption signal applied to the interruption receiving circuit. CONSTITUTION:Oscillator 9 which oscillates to generate a signal at constant intervals of time, and gate circuit 10 which ANDs the oscillation output signal with the all-ORed interruption signal of subfactors and uses the resulting output as an interruption signal to an interruption receiving circuit are provided. Then, if subfactors to be inputted to an extended interruption receiving circuit are generated successively in a short time and the congestion where an interruption can not be accepted normally with respect to the filter time constant of the input part of the interruption receiving circuit occurs, subfactor signals are temporarily released with the output signal of oscillator 10 and the operation of refeeding after a certain time determined by the period of the oscillator passes is repeated until the normal acceptance of an interruption is enabled.
JP4797080A 1980-04-14 1980-04-14 Interruption signal receiving circuit Granted JPS56145412A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4797080A JPS56145412A (en) 1980-04-14 1980-04-14 Interruption signal receiving circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4797080A JPS56145412A (en) 1980-04-14 1980-04-14 Interruption signal receiving circuit

Publications (2)

Publication Number Publication Date
JPS56145412A true JPS56145412A (en) 1981-11-12
JPS6217778B2 JPS6217778B2 (en) 1987-04-20

Family

ID=12790169

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4797080A Granted JPS56145412A (en) 1980-04-14 1980-04-14 Interruption signal receiving circuit

Country Status (1)

Country Link
JP (1) JPS56145412A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6045865A (en) * 1983-08-22 1985-03-12 Fujitsu Ltd Information processor
JPS6076448U (en) * 1983-10-26 1985-05-28 澤藤電機株式会社 Interrupt input circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6045865A (en) * 1983-08-22 1985-03-12 Fujitsu Ltd Information processor
JPS6359181B2 (en) * 1983-08-22 1988-11-18
JPS6076448U (en) * 1983-10-26 1985-05-28 澤藤電機株式会社 Interrupt input circuit

Also Published As

Publication number Publication date
JPS6217778B2 (en) 1987-04-20

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