JPS5590141A - Frequency control system - Google Patents

Frequency control system

Info

Publication number
JPS5590141A
JPS5590141A JP16499278A JP16499278A JPS5590141A JP S5590141 A JPS5590141 A JP S5590141A JP 16499278 A JP16499278 A JP 16499278A JP 16499278 A JP16499278 A JP 16499278A JP S5590141 A JPS5590141 A JP S5590141A
Authority
JP
Japan
Prior art keywords
circuit
control signal
local oscillation
pll
crystal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16499278A
Other languages
Japanese (ja)
Inventor
Tadaki Yamamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Marantz Japan Inc
Original Assignee
Marantz Japan Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Marantz Japan Inc filed Critical Marantz Japan Inc
Priority to JP16499278A priority Critical patent/JPS5590141A/en
Publication of JPS5590141A publication Critical patent/JPS5590141A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
    • H03L7/185—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using a mixer in the loop

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Transceivers (AREA)

Abstract

PURPOSE:To make it possible to lower the price while simplifying this circuit by reducing local oscillation crystal by adding or subtracting a constant number to or from a control signal through a logic circuit and then by applying the converted control signal to a program counter. CONSTITUTION:Control signal N of PLL is added or subtracted by logical operation circuit BC to vary the output frequency of PLL without varying local oscillation frequency f1. As a result, an arithmetic process can be carried out by an arithmetic instruction signal through logical operation circuit BC, and consequently only one crystal for local oscillation is required, so that the circuit can be simplified.
JP16499278A 1978-12-27 1978-12-27 Frequency control system Pending JPS5590141A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16499278A JPS5590141A (en) 1978-12-27 1978-12-27 Frequency control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16499278A JPS5590141A (en) 1978-12-27 1978-12-27 Frequency control system

Publications (1)

Publication Number Publication Date
JPS5590141A true JPS5590141A (en) 1980-07-08

Family

ID=15803773

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16499278A Pending JPS5590141A (en) 1978-12-27 1978-12-27 Frequency control system

Country Status (1)

Country Link
JP (1) JPS5590141A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6050235U (en) * 1984-07-19 1985-04-09 川崎重工業株式会社 offshore platform
WO1985004346A1 (en) * 1984-03-26 1985-10-10 Meiji Milk Products Company Limited Process for preparing w/o/w complex emulsion for medicinal and cosmetic use

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1985004346A1 (en) * 1984-03-26 1985-10-10 Meiji Milk Products Company Limited Process for preparing w/o/w complex emulsion for medicinal and cosmetic use
JPS6050235U (en) * 1984-07-19 1985-04-09 川崎重工業株式会社 offshore platform
JPS618115Y2 (en) * 1984-07-19 1986-03-13

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