JPS5530715A - Digital timer circuit - Google Patents

Digital timer circuit

Info

Publication number
JPS5530715A
JPS5530715A JP10227278A JP10227278A JPS5530715A JP S5530715 A JPS5530715 A JP S5530715A JP 10227278 A JP10227278 A JP 10227278A JP 10227278 A JP10227278 A JP 10227278A JP S5530715 A JPS5530715 A JP S5530715A
Authority
JP
Japan
Prior art keywords
output
time
counter
coincidence
cpu
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10227278A
Other languages
Japanese (ja)
Inventor
Takatomo Izume
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP10227278A priority Critical patent/JPS5530715A/en
Publication of JPS5530715A publication Critical patent/JPS5530715A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To enable the CPU to control the delay time of a shorter cycle than the time interruption cycle by providing the preset register which can be set by the CPU, the FF, the pulse counter and the coincidence circuit each.
CONSTITUTION: Numerical value A equivalent to the necessary delay time is set previously to preset register 2 from CPU1, and then trigger signal 6 is delivered to FF7. Then FF7 is set immediately, and output Q becomes 1 to turn clear input CL of up-counter 4 to 1. When the output pulse is supplied from pulse generator 5 of cycle Tp, contents B of counter 4 increases. And when the coincidence is obtained at coincidence detection circuit 3 between preset value A of register 2 and the value of counter 4, coincidence signal A=B is delivered to set FF7 and then to turn output Q to 0. Output 1 of FF7 is delivered through delay output 8 with time T. With the preset value set to A=Tp/T, the CPU can control the time limit of under the timer interruption time.
COPYRIGHT: (C)1980,JPO&Japio
JP10227278A 1978-08-24 1978-08-24 Digital timer circuit Pending JPS5530715A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10227278A JPS5530715A (en) 1978-08-24 1978-08-24 Digital timer circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10227278A JPS5530715A (en) 1978-08-24 1978-08-24 Digital timer circuit

Publications (1)

Publication Number Publication Date
JPS5530715A true JPS5530715A (en) 1980-03-04

Family

ID=14322955

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10227278A Pending JPS5530715A (en) 1978-08-24 1978-08-24 Digital timer circuit

Country Status (1)

Country Link
JP (1) JPS5530715A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5786924A (en) * 1980-11-20 1982-05-31 Nec Corp Timer device
JP2008270985A (en) * 2007-04-17 2008-11-06 Matsushita Electric Works Ltd Timer circuit and warning device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5786924A (en) * 1980-11-20 1982-05-31 Nec Corp Timer device
JP2008270985A (en) * 2007-04-17 2008-11-06 Matsushita Electric Works Ltd Timer circuit and warning device

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