JPS5652443A - Parity addition system - Google Patents
Parity addition systemInfo
- Publication number
- JPS5652443A JPS5652443A JP12686779A JP12686779A JPS5652443A JP S5652443 A JPS5652443 A JP S5652443A JP 12686779 A JP12686779 A JP 12686779A JP 12686779 A JP12686779 A JP 12686779A JP S5652443 A JPS5652443 A JP S5652443A
- Authority
- JP
- Japan
- Prior art keywords
- parity
- initial value
- signal
- adder
- addition
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Detection And Correction Of Errors (AREA)
Abstract
PURPOSE: To make it possible to easily detect abnormality by a parity check circuit when 1 addition is not executed, by setting the initial value of a 1 adder and a parity bit register PTR to such a pattern as becomes normal after 1 addition.
CONSTITUTION: The initial value of the bit groups C0WC6 is set to the adder 1 by an initial setting timing signal TC to the 1 adder 1, and at the same time the initial value 0 of a parity bit CP to the initial value is set by an initial setting timing signal TP to PTR2. A forecasting timing T1 provided to the parity forecasting circuit 3 is input through the gate 9, also a signal TC is delayed 8, an initial setting delay signal TC' is input to the gate 9, and a signal T1 is stopped only immediately after it has been initialized. As a result, when 1 has been added after initializing, a normal parity bit CP is output. In case 1 addition has not been executed normally after initializing, parity check is performed by the parity check circuit 7, and therefore abnormality is detected, and a trouble, etc. can be detected at an early state.
COPYRIGHT: (C)1981,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP54126867A JPS6017127B2 (en) | 1979-10-03 | 1979-10-03 | Parity addition method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP54126867A JPS6017127B2 (en) | 1979-10-03 | 1979-10-03 | Parity addition method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5652443A true JPS5652443A (en) | 1981-05-11 |
JPS6017127B2 JPS6017127B2 (en) | 1985-05-01 |
Family
ID=14945790
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP54126867A Expired JPS6017127B2 (en) | 1979-10-03 | 1979-10-03 | Parity addition method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6017127B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0758477B2 (en) * | 1987-01-07 | 1995-06-21 | ハネイウェル・ブル・インコーポレーテッド | Method and apparatus for verifying memory address integrity |
US5697710A (en) * | 1995-10-20 | 1997-12-16 | Nok Corporation | Bearing seals and bearing and seal assemblies |
-
1979
- 1979-10-03 JP JP54126867A patent/JPS6017127B2/en not_active Expired
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0758477B2 (en) * | 1987-01-07 | 1995-06-21 | ハネイウェル・ブル・インコーポレーテッド | Method and apparatus for verifying memory address integrity |
US5697710A (en) * | 1995-10-20 | 1997-12-16 | Nok Corporation | Bearing seals and bearing and seal assemblies |
Also Published As
Publication number | Publication date |
---|---|
JPS6017127B2 (en) | 1985-05-01 |
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