JPS5637573A - Integrated circuit with tracer memory - Google Patents

Integrated circuit with tracer memory

Info

Publication number
JPS5637573A
JPS5637573A JP11333779A JP11333779A JPS5637573A JP S5637573 A JPS5637573 A JP S5637573A JP 11333779 A JP11333779 A JP 11333779A JP 11333779 A JP11333779 A JP 11333779A JP S5637573 A JPS5637573 A JP S5637573A
Authority
JP
Japan
Prior art keywords
circuit
tracer memory
integrated circuit
logic
control circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11333779A
Other languages
Japanese (ja)
Inventor
Tsuyoshi Fukui
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP11333779A priority Critical patent/JPS5637573A/en
Publication of JPS5637573A publication Critical patent/JPS5637573A/en
Pending legal-status Critical Current

Links

Landscapes

  • Testing Of Individual Semiconductor Devices (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To reduce the number of connecting pins between the objective circuit and tracer memory, by incorporating the tracer memory in the integrated circuit.
CONSTITUTION: Every time when the logic operation is finished for the logic circuit 2 in the integrated circuit 1, the timing signal (t) is output from the timing generation circuit 4 in the logic circuit 2 to the control circuit 5, the control circuit 5 outputs the log signal (l) to the tracer memory 6, and the line state at the end of logic operation is logged in the tracer memory 6. If an error is taken place in the logic circuit 2, the error detection circuit 3 outputs the error signal (e) to the control circuit 5. The control circuit 5 outputs the log function stop signal (s) to the tracer memory 6.
COPYRIGHT: (C)1981,JPO&Japio
JP11333779A 1979-09-04 1979-09-04 Integrated circuit with tracer memory Pending JPS5637573A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11333779A JPS5637573A (en) 1979-09-04 1979-09-04 Integrated circuit with tracer memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11333779A JPS5637573A (en) 1979-09-04 1979-09-04 Integrated circuit with tracer memory

Publications (1)

Publication Number Publication Date
JPS5637573A true JPS5637573A (en) 1981-04-11

Family

ID=14609681

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11333779A Pending JPS5637573A (en) 1979-09-04 1979-09-04 Integrated circuit with tracer memory

Country Status (1)

Country Link
JP (1) JPS5637573A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56110162A (en) * 1980-02-06 1981-09-01 Hitachi Ltd Stage tracer
JPS60173648A (en) * 1984-02-17 1985-09-07 Panafacom Ltd Memory control system
JP2013178638A (en) * 2012-02-28 2013-09-09 Ricoh Co Ltd Image processing circuit, image processing device, and method for controlling image processing circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56110162A (en) * 1980-02-06 1981-09-01 Hitachi Ltd Stage tracer
JPS6321932B2 (en) * 1980-02-06 1988-05-10 Hitachi Ltd
JPS60173648A (en) * 1984-02-17 1985-09-07 Panafacom Ltd Memory control system
JP2013178638A (en) * 2012-02-28 2013-09-09 Ricoh Co Ltd Image processing circuit, image processing device, and method for controlling image processing circuit

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