JPS6017127B2 - Parity addition method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a parity addition method in a 1 adder.

In electronic computers, 1 adders are widely used that calculate plus 1 and output an output including a carry signal to the higher digits. Performing parity check.

FIG. 1 is a block diagram of a conventional 1-adder parity addition system, and FIG. 2 is an explanatory diagram of the operation sequence of FIG. 1. For example, CO
The initial value "0000000" of 7 bits of C6 is set in the 1 adder 1, and the odd parity bit value "1" of "0000000" is set in the parity bit register 2 by the initial setting parity timing signal Tp.
is set to

Next, the parity prediction timing signal TI and the 1 adder 7
Bit output CO~C6 and parity bit register 2
When the output Cp is input to the parity prediction circuit 3, the parity prediction circuit 3 predicts CO to C6 after the next 1 addition, and sends the parity prediction value Cp' = "0" at that time via the output line 6. Feedback to parity bit register 2.

Next, by applying the addition timing signal TO to 1 adder 1 and parity bit register 2, 1 adder 1
performs a plus-one operation and writes “000000” to the output bit line.
The parity bit register 2 sets the fed-back parity prediction value CP="0".

Again, according to the prediction timing signal TI, the parity prediction circuit 3 outputs the parity bit prediction value CP=“0” for CO to C6 after the next 1 addition, and the parity bit
Return to register 2. In this way, the values of the output values CO to C6 to be sent out and the parity bits Cp for them are input to the parity check circuit 7, where a parity check is performed to check that they are correct. In this way, in the circuit of FIG. 1, the 1 adder output bit group CO to C6 and the parity bit C before 1 addition
The parity bit after addition of 1 is predicted from the state of p, and it is determined whether parity bit register 2 needs to be inverted.

However, in the parity addition method shown in Figure 1, since the addition of 1 is performed after parity prediction, the initial value of the parity bit Cp is set to be normal to the initial values of all output bit groups CO to C6. It is necessary to do so.

Even if the timing signal TO to the 1 adder and parity bit register 2 is malfunctioning and parity prediction and 1 addition are not performed, the initial value is that the output bit group CO to C6 and the parity bit Cp are normal. Therefore, the initial value is checked as is in the parity check circuit 7, and the parity prediction and 1
This has the disadvantage that it is processed as if an addition had been executed, which delays the discovery of a fault.

In order to eliminate such drawbacks, it is an object of the present invention to provide a highly reliable parity addition method that allows a parity check to immediately detect an abnormality when 1 addition and parity prediction are not performed in a 1 adder. Our goal is to provide the following.

The parity addition method of the present invention includes means for setting the initial value for the parity bit register so that it becomes normal after adding 1, and means for blocking only the prediction operation of the parity prediction circuit immediately after the initial setting. After setting, first 1
It is characterized by performing addition.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 3 is a block diagram of a 1-adder equipped with the parity addition method of the present invention, and FIG. 4 is an explanatory diagram of the operation sequence of FIG. 3.

In the present invention, the values of CO to C6 are set to "0000000" by the initial setting timing signal Tc for the 1 adder 1.
1 is set in adder 1, and at the same time, the initialization timing signal Tp for parity bit register 2 initializes the parity bit Cp for the value ``0000000'' to be incorrect as odd parity. .

That is, the initial setting value of parity bit Cp is "0".
is set to Further, as shown in FIG. 3, the predicted timing signal TI applied to the parity prediction circuit 3 is inputted via a NAND gate 9.

The other input terminal of the NAND gate 9 receives an initial setting delay signal Tc' which is obtained by delaying the initial setting timing signal Tc until the delay circuit 8 outputs the predicted timing signal TI. The NAND gate 9 receives the initial setting delay signal Tc
' is "0", the gate is opened and the initial setting delay signal T
The gate is closed only when c' is "1" to block the predicted timing signal TI. Therefore, the parity prediction timing signal TI that is input at a constant period is blocked only immediately after the initial setting, and the parity prediction operation is not executed, and the initialized value Cp of parity bit register 2 = "OJ
is fed back to parity bit register 2 as it is as parity predicted value Cpr = "0", so the value of parity bit register 2 at the time of the first addition of 1 is not inverted and Cp = "0". Retained.

At this time, parity bit Cp becomes a normal value. That is, in the present invention, the parity bit Cp becomes normal only when it is incremented by 1 after initialization. After initial settings,
1 adder 1 executes a plus-1 operation according to the timing signal TO of 1 adder 1, and the value of output bit group CO to C6 is "0".
000001'' to the output line 4, and at the same time, the timing signal T causes the initially set Cp="0" to be fed back as is, the parity prediction value Cp'="0", to the parity bit register 2. Set and output Cp="0" to the output line 5.

The parity check circuit 7 checks the output bit group CO to C6 and the parity bit Cp after addition of 1, and confirms that they are normal. Further, after the addition of 1, the initial setting delay signal Tc' becomes "0", so the next parity prediction timing TI passes through the NAND gate 9 and is input to the parity prediction circuit 3.

By inputting the output bit group CO to C6 after addition of 1, the parity output Cp of the parity bit register 2, and the prediction timing signal TI, the parity prediction circuit 3
predicts the parity bit for the next 1 addition and Cb
="0" is sent to output line 6 and input into parity bit register 2.

If the 1-adder 1 or the 1-addition timing signal TO is not properly executed after the initial settings, the initial setting value is output as is and the parity check circuit 7 Since the parity check is performed at , abnormalities are detected there and early detection of failures becomes possible.

In other words, the value of the output bit group CO to C6 at the time of initial setting is "o
Since the parity bit Cp value "OJ" at the time of initial setting is outputted as "oooooooo", the error output ERR is given from the parity check circuit 7 which detects that the parity is incorrect as odd parity. Although the description has been made assuming that the bit parity is odd and the initial value is all "0", the number of bits may be arbitrary, and even parity may be used. Furthermore, the initial value is not limited to all "0", but can be any value that has incorrect parity, such as the correct parity being different between the initial value of the 1 adder and the value after 1 addition. As explained above, according to the present invention, the initial values of the 1 adder and the parity bit register are set to a pattern that becomes normal after 1 addition, so when the 1 addition operation is not performed, the parity bit register is - Abnormal conditions can be easily detected with a check circuit, and a highly reliable 1-adder can be realized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional parity addition method, FIG. 2 is an explanatory diagram showing the operation sequence of FIG. 1, and FIG. 3 is a block diagram of a parity addition method showing an embodiment of the present invention.
FIG. 4 is an explanatory diagram showing the operation sequence of FIG. 3. 1:1 adder, 2: parity bit register, 3:
Parity prediction circuit, 4:1 adder output line, 5: Parity bit output line, 6: Parity predicted value output line, 7: Parity check circuit, 8: Delay circuit, 9: NAND gate, TO: 1 addition operation timing signal, TI: parity prediction operation timing signal, Tc: 1 adder initial setting timing signal, Tp: parity bit register initial setting timing signal, CO to C6: 1 adder output bit group,
Cp: parity bit, Cb: parity prediction output, E
RR: Error output. Eagle' figure 2 groove 3 figure ticket 4 figure

Claims (1)

[Claims] A 1-1 adder, a circuit that predicts parity bits for all output bit groups of the 1-adder, and a parity bit that sets the parity bits based on the output of the parity prediction circuit.
In the parity addition method with bit registers,
The parity bit register is provided with means for setting the initial value for the parity bit register to become normal after adding 1, and means for blocking only the preliminary operation of the parity prediction circuit immediately after the initial setting. A parity addition method that is characterized by performing the following.