SU1605239A1 - Device for checking multiprocessor system - Google Patents

Abstract

The invention relates to computing and is intended to build reliable computing systems with built-in controls. The purpose of the invention is to expand the scope of application due to the possibility of controlling the passage of an arbitrary program without replacing the equipment in the system. The system comprises a processor 1, a block 3 of a memory device, a block 4 of external devices, a command register 6, a command strobe allocation unit 5, a control word register block 7, a control word generation unit 8, a control section counter block 9 and an indication unit 10. The command strobe allocation unit highlights the time at which the first word of the command is stored on the system bus, which is stored in the command register. The command code is applied to the control word formation unit and added to the previous value of the control word. The resulting control word is stored in the control word register block and can be read by the program and checked. The checkpoint counter block counts the number of program calls to the control word register block. If by the end of the program the number of references to the control word block does not correspond to the specified one, then the display unit generates an error signal. 3 hp ff, 7 ill.

Description

The invention relates to computing and can be used to build reliable computing systems with built-in controls.

The purpose of the invention is to expand the scope of application due to the possibility of controlling the passage of an arbitrary program without replacing the equipment in

the system.

 FIG. 1 shows a block diagram of the device; Fig. 2 is a block diagram of a command strobe block; FIG. 3 shows the structure of the control word register block; FIG. 4 shows a block of the form word for the control word; in FIG. 3, a block of the counter of control sections; FIG. 6b shows a timing diagram for the operation of the command strobe block allocation; 7 is a diagram of the command register and the control word register of the control word register block.

In the diagram (Fig. 1) there are: processor 1, system bus 2, storage unit 3 (memory), block 4 external devices (command unit), command strobe allocation unit 5, command register 6, control register register 7 words block 8 of forming a control word, block 9 of a counter of control plots, block 10 of indication

The command strobe unit 5 (FIG. 2) contains a permanent memory unit 11 (ROM), a subtracting counter 12, an AND 13 element, an OR-NOT 14 element, a delay element 15.

Block 7 of the control word register (FIG. 3) contains the main

transceiver 16, control word register 17, address selector 18, trigger 19, first element OR 20, OR-NOT element 21, second element OR 22, AND elements 23-25, delay element 26.

The control word formation unit 8 (Fig. 4) is the adder 27.

Block 9 of the counter of control sites (FIG. 5) contains a subtracting counter 28, the first: element AND 29, element OR 30, elements AND 31-33, trunk transceiver 34, address selector 35, trigger 36, delay element 37.

In order for the computing system to work reliably, reliable performance must be ensured.

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programs. However, in real conditions, normal program execution may be disrupted, as malfunctions, equipment failures, and other causes are possible. Therefore, it is important in the shortest time to detect the very fact of violation of program execution.

The proposed device monitors the programs executed in this computing system. The control is carried out by adding all the operation codes (modulo 256) and then programmatically comparing the result obtained with the previously calculated reference. In this system, it is assumed that the computing system has a configuration of the type Q-BUS, which is used in the Elektronika-60 micro-computer. This approach assumes the presence of a combined channel of the address and data. The system bus is control lines and shared address and data channels.

The device works as follows.

Block 5 of the strobe command release highlights the time at which the first word of the command is stored on the system bus 2, which is recorded in command register 6. The first word of the command, together with the predetermined value of the control word, is fed to the inputs of the control word generating unit 8. The result obtained by the signal received from the command strobe unit 5 is recorded in the control word register 17 of the control word unit 7. At any point in the program, this value can be read from register 17 of the control word of block 7 (this register is programmatically accessible) and the value of the control word is compared programmatically with the previously calculated one (the reference value of the control word can be calculated either manually or using a special program of the translator that added In the program text, special commands read the values of the control word and compare this value with the standard).

However, in the case of incorrect program execution, for example due to a processor 1 failure, a comparison of the standard and the checksum may not occur. For this case, the following mechanism is provided kontiol ..

At the very beginning of the program, in the counter of 28 control plots of block 9 of the counter of control plots, the number of control plots in the program is entered. The control section is the part of the program that ends with the operation of reading the control word and comparing it with a reference. During a program call to the control word register block, a program call signal is generated to the control word register, which is transmitted to the counter 28 of the control sections of block 9, where it is subtracted from the specified number of hits. In this case, after the normal execution of the program, the counter 28 of block 9 should contain O value, which triggers the display unit (for example, the LED is lit). Otherwise, for example, if processor 1 is malfunctioning, the LED will not be lit, which indicates a program execution error.

The structures of blocks 5–9 of the proposed device are given for cases of microelectronics electronics –60 M. When describing the operation of the proposed system, the following notation is used:

XIA - synchronization signal of the active device,

KSIP - a signal of synchronization of the passive device, KVVOD - data input KVYVOD - data output, KVU - output of the external device, XRAY - initial installation of the channel.

In block 5, the selection of the command strobe when the power is turned on in the above micro computers is generated by a channel signal of a general reset of the XRAY. On this signal, the subtracting counter 12 of the command strobe unit 5 is reset to O.

The first data, which is in the vehicle on the bus, will be the first command word, which will go to the input of ROM 11 of block 5, and the output of the ROM will have a code that determines how many instructions there will be memory access in this command. as in an arbitrary case it is impossible to separate the first command word from the operands. Therefore, from the first command it is necessary to track the time of occurrence of the first words of operation on the system bus. Thus, at the addresses corresponding to the codes of the first words of the commands, codes are written that determine the duration of the command in the system bus access cycles (how many cycles must be skipped in order to take into account

d only the next first word of the command). An example of such a correspondence is given: the first command word is the code for the number of calls to the system channel (bus). The CLRR1 team has

5 The first word is 005001 (the code value is given in the octal value). Since this command does not require additional access to the memory, and consequently, to the system bus, the value that will be located at address 005001 in ROM 11 will be 1.

The CLRUH # 1000 command (the octal code of the command 005037 001100) has the first word of the command 005037. This command needs another memory access, therefore the value in the corresponding cell of ROM 11 will be 2. After the reset in the subtracting counter

0 ke 12 will be the value of O, the output of the element And 13 will also be the value of O. Therefore, starting with the first command, and further in the case of the value of the counter O and negative

DU signal KVVOD on Wits signal For

the writing on the control input of the counter 12. By the same signal, the operation code is written to the register 6 of the command. At the end of each cycle, by the positive channel signal difference KSIA from the subtracting counter, 1 will be subtracted, which will provide its value O during the reception of the next operation code. The first word of the command will arrive

one of the group information inputs of the control word formation block 8, the second input will be supplied with the value coming from the register 17 of the control word of the block 7. Block

8 forming a control word is a combinational circuit. Therefore, the signal generated by the ophthalmic element OR 14 of block 5 passes through the delay element 15 (RC-chain), which takes into account the delay necessary for the formation of the control word in block 8 of form-; control word, and is strobe to record the received

the value of the control word in the register 17 of block 7. The timing diagram of the signals accompanying the described process of operation of block 5 is shown in Fig.6.

When programmatically accessing the control word register 17, block 7 operates as follows. The trunk transceiver is initially turned on to receive from system bus 2. Thus, if the system bus address matches the address of the control word register 17, then the output of the address selector 18 is logical one (the address selector is a circuit comparing code) . The logical result of the operation of the address selector for the CSIA signal is written to the trigger 19. The output of the trigger 19 is turned on by a register access enable signal. The signal from the trigger 19 in the case of a write operation (QUESTION) or reading (ESCRED) through the delay element 26 forms the response signal of block 7. The delay generated by the delay element is determined by the requirements of the time relationships. In the case of a programmatic read, the main transceiver 16 unit 7 switches to the direction from register 17 of the control word to the system bus 2. This is provided by logic element 24, the output of which is connected to the control input of the main transceiver 16. The possible execution of the register country 17 is presented in Fig.7. The control of such a register is provided by the Luster elements 20, 21 and 25. In the case of a programmatic access to the control word register 17, a signal is generated about the programmatic access to the control word register 17 by means of a logic element 24. This logic signal is fed to the control input of the detracting counter. 28 block 9.

Block 9 of the counter of control plots works as follows. At the beginning of the program, the counter 28, which is software accessible, records the value of the number of test sites. The signal coming from block 7 of the control word register (AND 24) is subtracted from the value of the code located in subtractive counter 28. Thus, at the end of the program,

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hOM is executed, its value stored in the counter should be equal to O. If not, the signal generated at the output of element 29 will trigger the display unit (LED lights up), which indicates a malfunction of the system. The operation of the trunk transceiver 34, the address selector 35, trigger 36 was considered in the description of block 7. Elements 30-33 and 37 are needed to synchronize the operation of the above elements.

Consider the constraints imposed on programming in this system. Dp providing the structure of any complex program, you can use a combination of three basic structures: Follow, Razvilka and Cycle. All data structures have one input and one output. The sums of the first words of commands in the general case and in different branches of these structures are different. Therefore, without additional measures, the control equipment at these sites can fix a program crash, which is virtually absent. In order for this not to happen, it is necessary to artificially align the amounts of the first words of the command (control words) in the branches of the structure to the same value before each merging of the branches. The alignment of the sums of the first words of a command can be easily performed as follows. In front of each merging point of the branches of the basic structures, additional commands are inserted, which enter into the register 17 of the control word of block 7 the corrected value of the control word. The typing of a control word can be accomplished with a single command. Since the summation of the first words of commands is performed over a certain module, for example, modulo 256, you can always specify a number that complements the sum to the desired value. The calculation of the correction values can be done either by the programmer or by using a special router, which calculates the correction value and inserts the necessary additional commands into the program. When using interrupt handling routines, you can use the following technique. At the beginning of the specified subroutines, the value of the control word is memorized.

and at the end of the execution of the subroutine is restored. The usual subprogram is subject to the same restrictions as the program as a whole.

These properties make it possible to expand the scope of application of the system, since, for example, in a well-known system, when replacing a program, it is necessary to replace the blocks of the permanent memory, and in the proposed system, when switching from program to program, the system hardware remains unchanged. Consequently, when using the proposed system, it is possible to control any prepared programs, and not one, as in the known system.

Claims (3)

1. A device for controlling a microprocessor system containing a control word generation unit, a command register, a control word register unit, information input and output of which are connected respectively to the output and the first information input of the control word generating unit, the second information input of which is connected to the output of the command register, information input of which is connected to the input of the device for connection to the system bus of the controlled microprocessor system, characterized in that expanding the field of application of the device due to the possibility of controlling the passage of an arbitrary program without replacing the hardware in the system, the device contains a command strobe block, a block of control sections plots and a display unit whose input is connected to the output of the control sections counter, the input-output of which is connected to the input-output of the device for connection to the system level of the controlled microprocessor system, the control input of the control section counter block is connected to the control output of the block Single control word register, whose input-output connected to the input-output device for connection to the system bus of microprocessor controlled system strobiru- yuschy input control word register unit connected to an output gate control word block vzdeleni 15 20 25 five The command strobe, the output of the command strobe of which is connected to the input of the register of the command register, the input of the command strobe isolation unit is connected to the input of the device for connection to the system bus of the controlled microprocessor system. 2. The device according to claim 1, about tl and - JQ, in that the command strobe allocation unit contains a fixed memory block, a subtracting counter, a delay element, an AND element and an OR-NOT element, the output of the OR-NOT element is connected to the input of the record of the subtracting counter, the output of the command strobe And through the delay element with the output of the control word strobe, the first input of the RSHI-NE element is connected to the discharge Input of the command strobe output of the command strobe, the second input of the OR element is NOT connected to the output of the AND element, whose inputs connected to a group of information outputs a melting counter, the group of information inputs of which are connected to a group of outputs of a permanent memory unit, the address input of which is connected to the information bits of the input of the command strobe selection block, the reset and subtraction counters of the counter are connected respectively to the reset and synchronization bits of the strobe output block . 3. The device according to claim 1, characterized in that the control word register block contains a control word register, an address selector, a trigger, a delay element, two OR inputs, an OR OR NOT element, three AND elements, and a trunk transceiver whose control input is disconnected to the output of the first element And the output of the control of the control word register block, the first group of inputs-outputs of the main transceiver is connected to the group of inputs of the address selector, the group of inputs-outputs of the register of the control word and the information output ode of the control word register block, whose information input is connected to the group of information inputs of the control word register, the first control input of which is connected to the output of the first OR element, the first input of which is connected to the gate input of the control register block 35 0 five 0 word, the second input of the first element OR, the second control input of the control word register and the input of the OR element are NOT connected to the output of the second element AND, the first input of which, the first inputs of the first and third elements AND are connected to the output of the trigger, information the input of which is connected to the output of the address selector, the input of the delay element is connected to the output of the third element AND, the second input of which is connected to the output of the second element OR, the first input of which and the second input of the first element AND are connected to the input of the input- The output of the control word register block, the second input of the second element OR, and the second input of the second element AND are connected to the discharge. The input / output of the control register register block, the synchronization bit of the input / output synchronization of which is connected to the trigger input of the trigger, the response of the output signal of the block output the control word register is connected to the output of the delay element, the second group of inputs and outputs of the trunk transceiver is connected to the information bits of the input-output block of the control word register, This control input of the control word register is connected to the output of the element OR NOT. 4, Device POP.1, characterized in that the block of the counter of control sections contains an address selector, a subtracting counter, a trigger, four AND elements, an element 5 o five 0 five 0 delays, the OR element and the main transceiver, the first group of inputs-outputs of which are connected respectively to the groups of information inputs of the address selector and deducting counter, the group of outputs of which is connected to the inputs of the first element I, the output of which is connected to the output of the counter block of control sections, the first inputs of the second , the third and fourth elements And are combined and connected to the trigger output, the information input of which is connected to the output of the address selector, the output of the second element And is connected to the account the input of the subtracting counter, the output of the third element I is connected to the input of the delay element, the output of the fourth element I is connected to the control input of the main transceiver, the second group of inputs and outputs of which are connected to the information bits of the input section of the counter of the control sections, Output, Synchronization input and the response signal of the input-output of which is connected respectively to the combined second input of the second element AND and the first input of the OR element, the combined second input of the OR element and the second entry in the fourth AND gate, the clock input trigger and the output of the delay element, an output of OR connected to the second input of the third AND gate, a control input vychitayu- Shchegrov counter connected to the control input of the control portions of the counter unit. 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