SU1068937A1 - Firmware control unit - Google Patents

Abstract

1. A MICROPROGRAM CONTROL DEVICE, containing the next 4Q command generation unit, the output of which is connected to the address input of the microcommand memory block, the output of which is connected to the information input of the microinstruction register; devices, characterized in that, in order to increase reliability by checking the correctness of the sequence of microinstructions in the microprogram, it additionally contains two delay elements, a second switch, a comparison unit, an error detection unit and a shift code register of the microprogram, the device control input connected to the first key input and the first control input of the next microcommand generation unit, the second control input of which is connected to the control input the microinstructions register, from the input of the first transponder element, to the second key input and to the key input through the second delay element. The output of the first delay element is connected to the first control input of the second channel the mutator, the information and second control inputs of which are connected respectively to the information and control outputs of the micro-register register, the first output of the second KOMMyTatopa is connected to the microprogram code shift register input, the output of which is connected to the first input of the comparator unit, the second input of which is connected to the second output of the code decoder microinstructions, the input of which is connected to the second output of the second switch, the output of the comparison unit is connected to the information input of the error detection unit, the output of which oedinen to the control input of the first KONwyTaTopa, a control input to the control output of the microinstruction register, and the third control input of the next microinstruction determination unit, an information input coupled to an address input device; 2. The device according to claim 1, wherein the block for determining the error contains two groups of elements AND, a group of elements OR, a group of triggers and an element OR ,; moreover, the information input of the block is connected to the first inputs of elements O AND of the first and second groups, to the second inputs of which 1k & 1e and inverse outputs from the group triggers are connected, respectively, to the reset inputs of which, besides the first, the outputs of the elements OR are connected , KjxjMe first, the output of which is connected to the single input of the first trigger; groups, outputs of elements AND of the first group, except the last, are connected respectively to single inputs of group triggers, except the first, output of the last element AND of the first group is connected to the first inputs of the elements OR groups j whose second inputs are connected to the control input of the block, outputs of the elements AND the second group connected to the inputs of the OR element, the output of which is connected to the output of the block.

Description

The invention relates to computing and can be used. It is designed to extend the functionality and increase the reliability of the operation of the computer control device.

A firmware control device is known that contains a microinstructions memory block, an address register, an address generation block, a micro-ops generation block, a control mode setting blocks and an L11 control block.

A disadvantage of this device is the lack of control over the correctness of following operations.

The closest to the present invention is a device comprising a regular micro-command generation unit, a micro-command memory block, a micro-command register, a micro-command code decoder, a switch, wherein the outputs of the next micro-command generation block are connected to the micro-command memory block outputs, and the decoder-micro code command outputs connected to the information inputs of the switch.

In order to increase the reliability of the device, the main blocks in it are reserved - the microinstruction register, the microinstruction memory block, the decoder, and the control register is entered. In the event of a failure of one of the main units, the backup units continue to work, ensuring reliable operation of the entire device 21.

However, in the known device, it is impossible to control the order of the following microcommands in the microprogram. If the order of micro-commands is violated, for example due to accidental failure of the control device equipment, no error will be detected, i.e. device will fail.

The aim of the invention is to increase reliability by controlling the correctness of the order of microcommands in the microprogram.

This goal is achieved by the fact that in the firmware control device containing the next microcommand generation unit, the output of which is connected to the address of the microcommand memory block, the output of which is connected to the microcommand register information input, the first output of the microinstruction code decoder output is output which is connected to the output of the device, introduced two delay elements, the second switch, the comparison unit, the error detection unit and the shift code register of the microprogram frame, and the control input of the device is connected to the first key input and the first control input of the next microcommand generation unit, the second control input of which is connected to the control input of the microcommand register, to the input of the first delay element, to the second key input and to the output key through the second delay element, the output of the first delay element is connected to the first control input of the second switch, the information and second control inputs of which are connected respectively to the information and control outputs the micro-commands register, the first output of the second switch is connected to the input of the shift register of the microporpaMNM code, the output of which is connected to the first input of the comparison unit; the second input of which is connected to the second output of the code decoder of the micro-commands, the input of which is connected to the second output of the second switch, the output of the comparison block is connected to the information input of the error detection unit, the output of which is connected to the control input of the first switch, and the control input with the control output of the micro-command register and the third control the main input of the definition of the next microcommand, the information input of which is connected to the address input of the device.

In addition, the error detection block contains two groups of elements AND, a group of elements OR, a group of triggers and an element OR, and the information input of the block is connected to the first inputs of the elements AND of the first and second groups, to the second inputs of which the direct and inverse outputs of the group triggers are connected , to the reset inputs of which, besides the first, are connected the outputs of the elements of the OR group, besides the first output of which is connected to the single input of the first trigger of the group, the outputs of the elements AND of the first group, except the last, are connected respectively Essentially, to the single inputs of group triggers, except the first, the output of the last element AND of the first group is connected to the first inputs of the OR elements of the group, the second inputs of which are connected to the control input of the block, the outputs of the elements AND of the second group are connected to the inputs of the OR element, whose pin is connected to the output block.

FIG. 1 is a block diagram of the device of FIG. 2 is a functional block of the error-determination unit, on the League. 3 shows the format of the firmware code; in FIG. 4 is a diagram of a comparison unit / in FIG. 5 - microcommand format. The device contains a regular micro-command block 1, a micro-command memory block 2, a key 3, a delay element 4, a micro-command register 5, a delay element 6, a switch 7, a micro-command code decoder 8, a microprogram code shift register 9., a comparison block 10, a block 11 determine the error and switch 12. Error definition block 11 (FIG contains a group of flip-flops 13, groups of elements AND 14 and 15, an element of IL 16, a group of elements OR I. Fornat microprogram code (FIG „3)” consisting of 4 microcommands , consists of 4 groups of 18-21 bits, first, second, - third and the fourth bits of which correspond to the operations of addition, subtraction of multiplication and division. Comparison unit (Fig. 4) contains groups of elements AND 22-26 and elements OR 23. The next microcommand production UNIT (IOMC) is a counter, information The input of which is the input of the device. This input receives the address of the command being executed. The first control input simultaneously with the address receives a control signal Address reception. The second control input is a counting input, and a +1 signal arrives at it. By the signal on the third ypravJJuyuyuyuyushchy input, the BYuMC is brought to its initial state. The TLOM is intended for the storage of micro-commands. The Register of micro-commands is intended for the storage of the micro-command read from the FBOMA. The control input of the PM receives a delayed signal 41, which permits the entry of an iro command into the given register. Switch 7 contains in its composition directly the switch and the trigger, controlled by the switch. The first control input is the setup input in the O trigger. The second control input of the CMIP is a trigger setup input. If the trigger is in a single state,. then the information from the CMIP is issued on the second information output, and in the opposite case - on the first code decoder (DC) the micro-man on the first output issues all micro commands, and on the second - only the result of the decryption of the micro-command transcript code. The proposed device operates as follows. The device's address is sent to the microprogram's address and the control signal. Address reception The microprogram address is the command operation code that is executed by this firmware. The address is fed to the entrance of the LCID. From the output of block 1, the address is fed to the BOMC. The information at this address is sent to the RMK. The permission to receive information in the RMK occurs on a delayed signal. Address reception. In the first cell corresponding to each firmware, it is not the micro-command that is stored, but the microprogram code that determines the sequence of micro-instructions that is executed on this microprogram. At the end of the execution of each firmware, the switch trigger 7 is set to one. Therefore, the firmware code from the PQM through the switch 7 is fed to the register 9. By the signal held by the element 4 by the reception of the address, the trigger of the switch 8 is set to the zero state. After element 4, the signal for receiving the address is also fed to the count input of the BPOMK and to the second key input. In the BOMC, the address of the first microcommand of the microprogram is formed, which is read from the PMOMK to the PMK. The signal at the output of the key passes through element 4 and controls reception at the PQM, and is also the +1 signal for TOMA. Since the trigger of the switch 7 is in the zero state, the microcommand from the RMK goes through it to the input of the DC. A microcommand consists of an operation code, an address part and a sign. The sign does not enter the DC, it is issued on the control output of the RMK. All microinstructions, except the last and. firmware code, the value of the attribute is zero. In the last microprogram of the microprogram, the attribute value is single. Therefore, after reading the last microcommand, the trigger 7 of the switch 7 is set to one and the TOMA and block 10 are reset. After the TLOMA is reset, it does not respond to the signal, + 1 until the arrival of the address reception signal. At the beginning of the first program, the Run command is executed, which consists of a single microcommand having a single sign state. This is done to install switch 7 in the trigger unit. After the entire microcommittee enters from the PQM to the DC, its operation code is decrypted and outputted to block 10, and the microinstruction enters the switch 12. In block 10, the microinstruction code is compared from the DC to firmware code.

The operation of the block 10 is as follows.

The code of the first microcommand defined in DC is compared with the code of bit 18 of the firmware code. In the case of (coincidence, a single signal is generated at the output. In the same way, comparison of the codes of the remaining microcommands takes place.

Signals are input to the circuit. The output signal of block 10 is a signal, O, allowing the output of information from block 11 ... Block 11 also includes a delay line (not shown) through which the Reset signal passes. If the codes are

the micro-command from the DC and register 5 matches, the first trigger 13 is set to +1. The second micro-commands set the second trigger 13, and so on. If the codes do not match in block 10, the next signal is not generated and the output of information from the switch 12 is prohibited.

Thus, the proposed device makes it possible to control the order of microcommands in the microprogram and thereby increase the reliability of the microprogram control device of the computer.

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Claims (2)

1. A MICROPROGRAM CONTROL DEVICE, comprising a unit for generating another micro-command, the output of which is connected to the address input of the micro-command memory block, the output of which is connected to the information input of the micro-command register, the first output of the micro-code decoder is connected to the information input of the first switch, the output of which is connected to the output of the device , characterized in that, in order to increase reliability by checking the correctness of the sequence of microcommands in the firmware, it additionally contains two a delay element, a second switch, a comparison unit, an error determination unit and a shift register of the firmware code, the control input of the device being connected to the first input of the key and the first input equal to the input of the next micro command generation block, the second control input of which is connected to the control input of the micro command register, from the input "! the first delay element, with the second key input and with the key output through the second delay element, the output of the first delay element is connected to the first control input of the second switch, the information and second control inputs of which are connected respectively to the information and control outputs of the micro-command register, the first output of the second switch is connected with the input of the shift register of the firmware code, the output of which is connected to the first input of the comparison unit, the second input of which is connected to the second output of the decoder to & a microinstruction having an input coupled to the second output of the second switch, the output of the comparator is connected to the data input of the error determining unit, whose output is connected to a control input of the first switch, and a control input to control output of the microinstruction register and a third control vho- house determination unit _Q another micro- $ command, the information input of which is connected to the address input of the device; 2. The device according to π. 1, wherein the error determination unit contains two groups of AND elements, a group of OR elements, a group of triggers and an OR element. moreover, the information input of the block is connected to the first inputs of the AND elements of the first and second groups, the second inputs of which are connected respectively yarn and the inverse outputs of the triggers of the group, to the reset inputs of which, in addition to the first, the outputs of the elements of the OR group are connected, except for the first, the output of which is connected to a single the input of the first trigger: groups, the outputs of the elements of the first group, except the last, are connected respectively to the unit inputs of the triggers of the group, except the first, the output of the last element of the first group is connected to the first inputs' of elements OR groups; the second inputs of which are connected to the control input of the block, the outputs of the AND elements of the second group are connected to the inputs of the OR element, the output of which is connected to the output of the block. and ..... 1068937