SU966694A1 - Microprogramme control device with transition - Google Patents

Description

(5) FIRMWARE CONTROL DEVICE WITH CONTROL RONES

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The invention relates to software control for detecting errors in the order and control of firmware, in particular to devices with permanently Attached firmware.

A device is known that contains a program's memory device, an account: command address cheek, command register,; device modification of the address of the matching scheme, convolution schemes for nrad 3

In the known device, the monitoring of the progress of the program on the human resources is phased: first, the formation of the command address is controlled; let us count П |: otodits control the correctness of treatment for ad-.

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The need to memorize the control codes of the command address causes an increase in the discharge of all the words of the memory device, and to control the formation of the command address

additional control code generation schemes are needed.

In addition, the disadvantage of this device is the low ability to detect errors that violate the normal course of the program. The closest to the proposed invention is a firmware with a transition control containing a block, microinstructor memory, address register, microinstruction register, a comparison block, a transition control block and a shift register 2. A fundamental drawback of the device is the inability to control false transitions between the sections with with the same configuration and, as a result,.: - complete coincidence of control codes, as well as difficult control of the part 20, which have convergent or parallel branches of the microprogram with ary configuration, that is required for complement "tive amount control mik396 rokomand, resulting in a significant reduction in operating speed. The purpose of the invention is to enhance the functionality of the device by increasing the reliability of transition control, reducing the time to detect failures and increasing speed by not using control microcommands. The goal is achieved by introducing a transition-control microprogrammed control device containing a microcommand memory block, an address register, a microcommand register, a comparison circuit, and a transition control block, the information output of the transition control block being connected to the first information input of the address register, the output of which connected to the microcontroller's memory input, informational microcontroller information output connected to the microinstructions register information input, the first output of which is With the second information input of the address register, the output of the comparison circuit is the signal output of the device, an associative memory block, a control register, a pulse distributor, an AND element and an OR element are inputted, the read input of the associative memory block is connected to the information output of the transition control block , the address input of the associative memory block is connected to the first output of the microinstruction register, the information output of the associative memory block is connected to the information input of the control register, the input is entered and which is connected to the output of the element OR, the first input of which is connected to the output of the element AND, the second input of the element OR is connected to the input of the initial setup of the device, the output of the control register is connected to the first input of the comparison circuit, the second input of which is connected to the output of the address register, the third input of the comparison is connected to the resolution output of the transition control unit and the first input of the element I, the second input of which is connected to the first output of the distribution

pulse divider, the second, third and fourth outputs of which are connected to the inputs of the entry of the register of micro-commands, the comparison circuit and. the address register, the setup input of the comparison circuit and the setup inputs of the micro-register register, the address register and the pulse distributor are connected

complemented to the microcommand's address part when calculating the address of the next microcommand in register 2 of the address and selecting the control address from block 6 of the associative memory.

From the third output of the register 3 microinstructions to the input 17 of the control module C with the input of the initial installation of the device. The reliability of the control is increased due to the fact that the principle of control in the proposed device eliminates situations where a false transition may not be detected. In addition, shortening the detection time for malfunctions is associated with more frequent checking of the correctness of following the microprogram and improving the speed by eliminating control microcommands from the microprogram. FIG. 1 shows a diagram of the device; in FIG. 2 is a diagram of a transition control unit; in fig. 3 is a comparison circuit; in fig. 4 is a diagram of the distributor; in fig. 5 is an example of a firmware algorithm executed by a device. The microprogram control unit with transition control contains a block of 1 microinstructor memory, a register of 2 addresses, a register of 3 microcommands, a block 4 of transition control, a comparison circuit 5, a block 6 of associative memory, a control register 7, elements 8 AND 9, OR, a pulse distributor. The output of block 1 of memory microinstructions. connected to the register input of 3 microinstructions. From the first output of the register 3 microinstructions, the operational part of the microcommand is transmitted to the output 14 of the device, into which the second micro-orders are encoded, affecting the system controlled by the firmware. The address part of a microcommand without a low-order bit from the fourth output of the register 3 micro-commands arrives at the address inputs of the register 2 addresses and block 6 of the associative memory. The low-order bit of the address part of the micro-command from the second output of the register 3 micro-commands is fed to the input 15 of the transition control unit C. From the output 18 of the transition control block, connected to the first address inputs of the address register 2 and the associative memory block 6, the lower-order address is set. The 5Ebb transitions are given the number of one of the tested conditions, the values of which are transferred from the operational schemes controlled by the firmware device to the input of the transition control unit from the 5th input 12 of the device. The control output 1b of the transition control unit i is connected to the input of the element 8 And and the enable input 27 of the comparison circuit 5. The output of the associated memory block 6 is connected to the information input of the control register 7, the output connected to the information input 2k of the comparison circuit 5. The output of the address 2 register is connected to the input of the microcommand memory block 1 and another information input 25 of the comparison circuit 5, from the output of which an error signal arrives at the output 13 of the device. The input of the register 7 control is connected to the output of element 9 OR, one input of which is connected to the output of element 8 AND, and the other is connected simultaneously to the inputs 19 and 28 of the initial installation of the distributor 10 and the comparison circuit 5, the corresponding inputs of the address register 2 and the micro-command register 3 and connected to the input 11 of the initial installation of the device. The first 20, the second 21, the third 22, the fourth 23, the outputs of the distributor 10 are connected, respectively, to the second input of the element 8 I, the register entry register 3 microcommands, the input 26 entry of the comparison circuit 5 and the address register entry 2 of the address. Transition Control Block Q (Fig. 2) contains a decoder 29, a group of elements 30 And, the number of which in the group is equal to the number of the analyzed logical conditions (n) plus. One element 31 OR and element 32 NOT. The first input of the first element 30 I is connected to the input 15 of the transition control unit k, and the first inputs of the remaining (n) elements 30 I are connected to the corresponding inputs 12 of the logic conditions. The other inputs of all (n + 1) elements 30 And are connected to the corresponding outputs of the decoder 29. In addition, the first output of the decoder 29 through the element 32 is NOT connected to the control output 16 of block t. The outputs of all elements 30 And connected to the inputs of the element 31 OR, the output of which is connected to the information output 18 of the block t. The information inputs of the decoder are connected to the input 17 of the block C. The comparison circuit 5 (Fig. 3) contains a circuit 33 coinciding with the information inputs connected to the inputs 24 and 25 of the comparison circuit 5, element 3 And trigger 30. The inputs of element 3 And are connected to the inputs 27 of the entry, 6 of the initial installation and the output of the circuit 33 match. The output of the element 3 And is connected to the installation input of the trigger 35, the reset input of which is connected to the input 28 of the comparison circuit 5. trigger 35 is connected to output 13 of the device. The coincidence circuit 33 can be built on elements I. The distributor 10 (FIG. A) contains a clock pulse generator B, a binary counter 37 and a decoder 38. The output of generator 36 is connected to the counting input of counter 37 and to the gate inverse of the decoder 38. Counter output 37 connected to the information input of the decoder 38, from which output the sync series arriving at the outputs 20, 21, 22 and 23 of the timing distributor 10 are removed. The reset input of the counter 37 is connected to the input 19. In FIG. 5 characters A; Marked microcommands in which conditional transitions are made. The symbol M is marked with a microinstruction in which no conditional transition is performed. The device works as follows. The principle of operation of the device is based on the fact that when the firmware is executed at the points of conditional jumps, the current address contained in the register 2 addresses is compared with the control one stored in register 7 of the control. The selection of the control address from block 6 of the associative memory and its entry into the control register 7 for the current transition are made upon executing the previous transition. Simultaneously with the control on the current re; One of the associative memory block 6 is selected and entered into the register 7 control address for use in the next transition, and so on. The only exception is the first conditional transition in the microprogram, since it has no previous one. For this, the control address is prepared by the initial setup signal. The comparison of the current address with the control one is carried out in the comparison circuit 5, which, in the event that the indicated addresses do not coincide, produces an error signal.

Consider the operation of the device on the specific example of the implementation of the firmware algorithm (Fig. 5).

The initial setup signal, which is fed to the device input 11, establishes 8 zero registers 2 addresses and 3. micro-instructions, counter 37 in the distributor 10 and trigger 35 in the comparison circuit 5. In addition, the initial installation signal through item 9 OR makes the entry of the control address into the control register 7, which is necessary to control the correctness of the passage of the microprogram when the transition A. is performed. .

Consider in more detail this moment.

At the beginning of the generation of the initial setup signal, the register of 3 micro-instructions is set to zero. At the same time, the code of the number of the condition being checked, coming from the third output of the register of 3 micro-instructions to the input 17 of the transition control block 4, is zero. Then the resolving unit potential is generated only at the first output of the decoder 29 in the transition control block 4 and thus connects to the information output 18 of the latter through the first element 30 And element 31 and OR the signal from input 15, which receives the lower part of the address microcode from second register output 3 microinstructions. As a result, the address inputs of the associative memory unit 6 receive a zero address equal to zero, at which the control address is selected; the address for the first transition in the firmware and enters the information input of the control register. The initial setup signal has a much longer duration than the sampling time from the memory. This is due to the fact that this signal is usually generated by pressing the corresponding key, and in addition, its duration is not related to time relationships when the device is operating. As a consequence, the control address for the first transition in the firmware will have time to be selected from block 6 of the associative memory. After the initial setup signal has expired, it will be entered into the control register.

At the end of the initial setup signal, the distributor 10 starts

to develop at their outputs 20-23 four shifted relative to each other sync series. The sync pulse from the output 20 of the distributor 10 is fed to the input of the element 8 I, however, it is not registered in the control register 7, because the element 8 I is blocked at another input by an inhibitory zero potential from the control output 16 of the transition control unit 4. This is due to the fact that at the input of the element 32 NOT in the transition control unit there is a resolving potential from the first output of the decoder 29. The sync pulse from the output 21 of the distributor 10 is recorded from the memory module 1 of the micro instructions in the register 3 of the micro instructions of the first micro command selected at the zero address in the register 2 addresses. In this case, it is a microcommand A,. Since there is a conditional transition in this microcommand, from the third output of the register 3 microcommands to the input 17 of the transition control block is non-zero, the number of the condition by which this transition must occur, as a result, the enabling signal is generated on one of the outputs of the decoder 29 except the first one in the block the transition control and the information output 18 of the latter receives a signal corresponding to the condition. Then the address of the next microcommand in register 2 of the address and the address of the control word in block 6 of the associative memory are modified depending on the value (O or 1) of the condition received from information output 18 of block i of the transition control i to the low-order input of address 3 and block 6 , thereby determining one of the two firmware continuation addresses. Since the first output of the decoder 29 in the transition control unit k has a forbidden potential, a control potential is generated at the control output 16 of the block k and is fed to the enable input 27 of the comparison circuit 5, the information inputs of which already have the current and control addresses being compared. If the addresses match, then the match circuit 33 outputs the element. 3 And the forbidding potential, if not the same, is the opposite. Therefore, when a pulse arrives from the output 22 of the distributor 10 to the input 26 of the input of the circuit 5 and the failure of the checked addresses from the output of the element 3, the signal sets the trigger 35, and the output 13 of the device detects an error. If the addresses are equal, no signal is generated. five

The sync pulse from the output 23 of the distributor 1 O into the register 2 of the address is entered into the address of the next microcommand. Depending on the condition value from the information output 18 of the k block, this is 0 microcommand M or microcommand At ,. From block 6, by the address part of the microcommand from the fourth output of the register of 3 microcommands and the value of the logical condition, the control address for 15 transition A2 or for transition A is selected. This completes the execution cycle of the first micro command.

In the next cycle, a pulse from the output 20 of the distributor 10 takes place 20 entering the control address into the control register 7, since element 8 I is opened by the resolving potential from the control output 16 of block 4.

The impulse from the output 21 distribute-25 l 10 the next micro-command is entered into the register of 3 micro-commands. This is the microcommand M. or A. Since the microcommand M is not a microcommand of a conditional transition, the field but-jo is a measure of the condition in it is zero. As a result, similarly to that described at information output 18 of block 4, the low-order bit of the address part of the microcommand is fed from the second output of register 3, and at the control output 16 of the transition control block produces a suppressive potential. The impulse from the output 22 of the distributor 10 does not cause any actions in the comparison circuit 5, since at its input 27 there is a inhibitory potential. Since when micro-command M is executed, the low-order bit of the address part of the micro-command is present at output 18 of the block, then from the output 23 of distributor 10 the address uniquely defining the micro-command is entered into register 2 ...

In the next third cycle, the pulse from the output 20 of the distributor 10 is entered into the register 7 of the control, since element 8 And is closed by the inhibitory potential from the output 16 of lock k. This prevents distortion of the control address in register 7 formed when micro-command A is executed. Next, the pulse from output 21 of the distributor 10 micro-command A is entered into the register 3 micro-commands and the further operation of the device is similar to the operation of the device when micro-command A.

If in the second cycle, the pulse from output 21 of the distributor 10 is entered into register 3 of the micro-command micro-command A-3, then since micro-command A, like micro-command A, is a micro-command of the conditional transition, the code of the condition number in it is non-zero. As a consequence, the signal at the control output 16 of the block k remains in the permitted state, and the information output 18 of block 4 receives the value of the logical condition in accordance with the number that arrives at input 17 of the transition control block C. Further, the operation is similar to the operation when executing micro-commands A and A. If in the prototype a false transition between microprogram sections with the same configuration remains undetected due to the coincidence of their control codes, then in the proposed device this situation is completely eliminated due to the fact that, unlike the prototype is not carried out on separate parts: firmware, but at each transition point; In addition, each transition corresponds to a well-defined micro-command, determined by the contents of the address register and having a certain value of the address part, as a result of which the control address of the next transition is selected from the associative memory block. Therefore, in the case of a false transition, the microcommand address, in which the next transition takes place, will always be different from the control one.

In addition, the device uses a control that is completely independent of the configurations of the firmware algorithms, in contrast to the prototype, where it is impossible to determine the code of the control microcommand when controlling the sections with converging or parallel branches of the microprograms, as a result each branch, which leads to a significant decrease in speed.

Claims (2)

In the proposed device, a failure in the current transition is already detected in the next transition, in contrast to the prototype, where a failure is detected only 11 at the end of the segment, which may have a large number of transitions. As a result, in the proposed device, the detection time of a failure is reduced several times, and therefore, the amount of unproductively lost microprogram execution time is also reduced. In addition, the exclusion of control microcommands from the microprogram improves the speed of the device. Claims - A firmware control device with transition control containing a microinstructor memory block, an address register, a microinstruction register, a comparison circuit and a transition control block, the information output of the transition control block connected to the first information input of the address register whose output is connected to the address the input of the micro-command memory block, the information output of the micro-command memory block is connected to the micro-command register information input, the first output of which is connected to the second address register output, the output of the comparison circuit is the signal output of the device, which is so that, in order to expand the functionality of the device, by increasing the reliability of control of transitions, reducing the time for detecting failures and improving performance by failure to use control microinstructions, an associative memory block, a control register, a dispenser gi of pulses, an element are entered into the device; And the OR element, the read input of the associative memory block is connected to the information output of the transition control block, the address input of the associative memory block is connected to the first output of the microinstruction register, the information output of the associative memory block is connected to the information input of the control register, the entry of which connected to the output of the OR element, the first input of which is connected to the output of the AND element, the second input of the OR element is connected to the input of the initial setup of the device, the output of the control register of the connection En with the first input of the comparison circuit, the second input of which is connected to the output of the address register, the third input of the comparison circuit is connected to the output of the resolution of the transition control unit and the first input of the element I, the second input of which is connected to the first output of the pulse distributor, the second, third and quarter IV outputs which are connected to the inputs of the entry of the register of microinstructions, the comparison circuit and the address register, the installation input of the comparison circuit and the installation inputs of the register of microinstruction, the address register and the distributor pulses are connected to the input of the initial installation of the device. Sources of information taken into account in the examination 1. NDPuzhintsev. Hardware control of digital computers. M ,, Soviet Radio, 1966. with. 36A. . 2. USSR author's certificate N ° 711573, cl. G About F 9/22, G About F 11/00, 1977 (prototype).