SU1020826A1 - Microprogram control device - Google Patents

Description

the first memory block, the output of the third element And is connected to the input, the counter of microcommands, the counting input of which is connected to the counting input of the address estimator and the output of the fourth And element, whose input is connected to the inverse output of the trigger, the input of the initial installation of the device connected to the inputs reset of microinstructions counter, trigger, register of logic conditions and buffer register,

 1, The invention relates to computing and can be used in the construction of digital computers.

A firmware control device is known that contains two memory blocks, two decoders, an address register and an address counter, a buffer register, a logic condition register, a microinstruction counter, an encoder, And elements and delay elements l.

The disadvantage of this device is the low productivity, due to the tbm, that during each transition from one sequence of microinstructions to another, the microcommand cycle is used non-conductively.

Closest to the proposed technical entity is a firmware control device containing the first group of elements AND whose outputs are connected to the first inputs of the buffer register, the output connected to the first inputs of elements AND of the group, the outputs of which are connected to the first inputs of the address register. The output of the address register is connected to the first input of the first decoder, the output connected to the address input of the first memory block, the first output of which is connected to the second input of the buffer register, and the second output to the first input of the microinstruction counter. The output of the microinstruction counter is connected through the first element I to the first input of the second element I, the output of which is connected to the second inputs of the elements AND of the second group. The third output of the first block

The memory is connected to the first input of the address counter, the output of which is connected via the second decoder to the address input of the second memory block, the first output of which is the output of the device, and the second output is connected to the second input of the micro-command counter and the second input of the address counter, the zero setting input connected to the second input of the first decoder, the input of the zero setting of the buffer register and the output of the third element. And, the first input of which is connected to the output of the first element And through the element NOT to the first input of the fourth element And at the same time the second input of the second element And is connected through the delay element to the second input of the third element And and the output of the second delay element, the input of which is connected to the generator output clock pulses and the second input of the fourth element And the output connected to the second input of the second decoder. The fourth output of the first memory unit is connected to the input of the zero setting of the address register, the second input of which is the input of the operation code of the device, the first inputs of the AND elements of the first group are the inputs of the logical conditions of the device. The input to the zero register of logical conditions is connected to the output of the third element I, the information input to the output of the logical conditions decoder, the inputs of which are connected to the second and third outputs of the first memory block, while the outputs of the register of logical conditions are connected to the second inputs of elements AND of the first group 2 A disadvantage of the known device is low productivity. This is due to the fact that during each transition from one sequence of execution of microcommands to another, control words are rewritten from the first memory block to the registers and counters of the device. In this case, each time, the micro-command CYCLE is unproductively expended. The purpose of the invention is to increase the productivity of the device. The goal is achieved by the fact that a firmware control device containing the first and second memory blocks, the address register, the buffer register, the logic conditions register, the address counter, the microinstruction count, the first and second groups of elements AND, the group of elements OR, the first, the second, third and; the fourth AND elements, the NOT element, the delay element and the clock pulse generator, the output of the number of microcommands of the first memory block connected to the information input of the microinstruction counter, the output of which through the first element AND connection n the first input of the second element I, the second input of which is connected to the first inputs of the third and fourth elements I and the output of the clock generator, the address output of the first memory block is connected to the information input of the address counter whose output is connected to the / address input of the second memory block ti, the output of the logical conditions of the first block of the mi ti is connected to the information input of the register of logical conditions, the output of which is connected to the first inputs of the AND elements of the first group, the upper inputs of which are connected to the input of the conditions The outputs and outputs are connected to the first inputs of the elements of the IL group, the second inputs of which are connected to the input of the operation code of the device and the outputs are connected to the installation input of the buffer register, the output of which is connected to the information input of the address register, the output of which is connected to the address input of the first block the memory, the output of the indirect address KOTdporo is connected to the information input of the buffer register, the output of the third element AND is connected to the input of the entry of the register of the address, the output of the third element And is connected to the inputs of the entry of the address counter, bu fer- The second register and the register of logical conditions additionally introduced a third group of elements AND, the second group of elements OR and a trigger, whose information input is connected to the output of the first element AND, the input of the input — with the generator output takBOBJX of pulses, and the direct output — with the second input of the third element Both with the input of the delay element, the output of which is connected to the first inputs of the elements of the second group and through the element is NOT connected to the first inputs of the elements of the third group, the second inputs of which are connected to the output of the second memory block and the outputs with the first inputs of the OR elements of the second group, the outputs of which are the operating output of the device, the second inputs of the OR elements of the second group are connected to the outputs of the AND elements of the second group, the second inputs of which are connected to the operational output of the first memory block 1, the input of the third element AND connected to the input of the entry of the micro-command counter, the counting input of which is connected to the counting input of the address counter and the output of the fourth element I, whose input is connected to the inverse output of the tri1-ger, the input of the initial installation of the device The event is connected to the input: the reset of the microinstructor counter, the trigger, the register of logical conditions and the buffer register. Figure 1 presents the scheme of the device; in fig. 2 - time diagram of the device. The microprogram control device contains a register of logical conditions, a group of elements I2, input 3 of which is an input of conditions of a device, a group of elements OR k, input 5 of which is an input of an operation code of a device, a buffer register 6, register 7 of address, block 8 of memory, a group of elements AND 9, a group of elements OR 10, the output 11 of which is the operational output of the device, a delay element 12, a element NOT 13, a group of elements AND AND, a microcode instruction counter 15, elements AND 16-19, an address counter 20, a memory block 21 , trigger 22, generator 23 pulses and input 2 initial installation. Figure 2 shows the timing diagram of the device, where 25 is the signal at the output of the element And 16; 26 pulses at the output of the generator 23 pulses; 27 - signal at the output of the Vepa 22; 28 - the signal at the output of the element 12 delay; 29 - pulses at the output of the element And 17; 30 pulses at the output of the element And 18; 31 - pulses at the output of the element And 19; 32 codes of microinstructions on output 11 of the device.

The device works in the following way.

To bring the device back to its original state, input 2 is fed

ts is the initial setup signal, in which the buffer register 6, the logical condition register 1, the microinstruction counter 15 and the trigger 22 are set to zero.

20

The input 5 of the device is given an operation code, which is fed through a group of elements OR k to the setup input of the buffer register 6 and sets the starting address of the firmware.

25 Since the contents of the 15 micro-instructions counter are zero, the signal 25 has a single value.

The pulse generator 23 produces a pulse 26, according to which pulses 29 and 31 are generated, and the trigger 22 at a single value of the signal 25 is set to one (all actions in the device are performed on the falling edges of the pulses). Signal 27 takes a single value. 35

Pulse 31 produces a reduction in the unit content of the counter of 15 commands, with the result that signal 25 takes a zero value.

40 According to pulse 29, the starting address from buffer register 6 is rewritten into address register 7, however, the micro-command output of memory block 8 appears after time t determined by e45 the memory sampling time. At the same time, at the output of the delay element 12, a single signal 28 is produced, according to which the group of elements AND 9 is opened. The group of elements and C closes.

50 by the signal from the output of the element NOT 13C of the first output of the block of memory 8 to the information input of the counter 15 micro-instructions the code, the value

55 which is one less than the number of microinstructions in the current sequence. From the second output of the memory block 8 to the information input from, the 20

the address receives the address of the second microcommand of the current sequence: From the third output of memory block 8, the code of logical conditions that are checked during the implementation of the current sequence arrives at the information input of the register 1 of the logical conditions. From the fourth output of the memory block 8, the indirect address of the first microcommand of the following sequence is fed to the information input of the buffer register 6. From the fifth output of the memory block 8, through the groups of elements AND 9 and OR 10 to the output 11 of the device, the operational part of the first microcommand M, the current sequence (pos.32). In the operational part of the microcommand, micro-orders are coded, effecting the system that is not controlled by the firmware.

The next pulse 26 produces a pulse 30, and the trigger 22 is set to zero. By impulse 30, control words: from the outputs of memory block 8 are rewritten into the registers and counters of the device. After the time b is in accordance with the zero value of the signal 27, the signal 28 also takes a zero value, as a result of which the group of elements AND 9 closes and the group of elements AND Ik opens. Based on the contents of the address counter 20, the operational part of the second microcommand M2 is selected from the memory block 21. The current sequence. The code of the operating part of the micro-command M2 through the groups of elements AND AND AND OR 10 is fed to the input 11 of the device (position 32).

Upon receipt of each next pulse 26, a pulse 31 is generated, which is used to change the content of the microcommand counter 15 and the address counter 20 by one unit. In accordance with the value of the address s, the counter 20 of the address from the memory block 21 reads the next microinstruction and enters the output 11 of the device. In the process of performing the current sequence of micro-instructions, the signals of logical conditions are received at the input 3 of the device from the ynpas-v system. The signals from the output of register 1 of logical conditions open the corresponding elements AND of the group of elements AND 2, the signals from the outputs of which through the group of elements or k change the address on the buffer register 6.. If, upon receipt of the next pulse 31, the contents of the microcommand counter 15 are equal to zero, then the signal 25 takes a single value. At the same time, according to the contents of the counter-20, the address from memory block 21 is read and the last microcommand of the current sequence arrives at output 11 of the device 11 (pos. 32 When the next impulse 26 arrives, the flip-flop 22 is set to one, and by impulse 29 the address from the buffer register 6 rewritten to address register 7. At this address, a control word is read from memory block 8 and fed to the information inputs of the device registers and counters. A single value of signal 28 opens a group of elements AND 9 and output II of the device J L- 1-

fig1

7 / H. TRK 268 the operational part of the first microcommand of the leading sequence is transmitted from the fifth output of the memory block 8. Further, the operation of the device is carried out similarly to that described above. Thus, the proposed device allows transitions from one sequence of microcommands to another without loss of time for overwriting control words into registers and counters of the device, unlike the protrusion type, where each time the microcommand cycle is not productively consumed. The proposed device allows transitions from one sequence of execution of microcommands to another without loss of time for rewriting control words necessary for performing a new sequence of microcommands. P p p p p „P P I 1 1 iii" 1 1 I Ml mg mz mp-1 f

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Claims (1)

FIRMWARE CONTROL DEVICE, containing the first and second memory blocks, address register, buffer register, logical condition register, address counter, micro-instruction counter, the first and second groups of AND elements, the group of OR elements, the first, second, third and fourth elements AND, the element NOT , a delay element and a clock pulse generator, and the output of the number of microcommands of the first memory block is connected to the information input of the microcommand counter, the output of which through the first element And is connected to the first input of the second element And, the second the path of which is connected to the first inputs of the third and fourth AND elements and to the output of the clock pulse generator, the address output of the first memory block is connected to the information input · an address counter, the output of which is connected to the address input of the second memory block, the output of the logical conditions of the First memory block is connected to the information the input of the register of logical conditions, the output of which is connected to the first inputs of the elements' AND • of the first group, the second inputs of which are connected to the input of the conditions of the device, and the outputs are connected to the first .. odes of elements OR groups, the second inputs of which are connected to the input of the device operation code, and the outputs are connected to the installation input of the buffer register, the output of which is connected to the information input of the address register, the output of which is connected to the address input of the first block of memory; which is connected to the information input of the buffer register, the output of the second element And is connected to the input register address, the output of the third AND element is connected to the inputs of entering the address counter of the buffer register g and the logical register; the conditions, which are related to the fact that, in order to increase productivity, a third a group of AND elements, a second group of OR elements, and a trigger, an information input [which is connected to the output of the first AND element, an input of entry - with the output of a clock generator, * and a direct output - with the second input of the third AND element and with the input of the delay element, whose output is connected to the first elements and passages of the second group and through the element is coupled to the first inputs of AND gates of the third group, the second inputs of_;which are connected to the output of the second memory block, and the outputs to the first inputs of the OR elements of the second group, the outputs of which are the operational output of the device, the second inputs of the OR elements of the second group are connected to the outputs of the AND elements of the second group, the second inputs of which are connected to the operational output 1020326 of the first memory block, the output of the third AND element is connected to the input of the micro-counter counter, the counting input of which is connected to the counting input of the address counter and the output of the fourth And element, the input of which is connected to the inverted output of the trigger, the input of the device initial installation • is connected to the reset inputs micro-counter *, mand, trigger, register of logical conditions and buffer register.