SU1159020A1 - Versions of microprogram control device - Google Patents

Abstract

1. An interprogrammed control unit containing a memory block, a microc register (RANDER, an address counter, a logic conditions multiplexer, and a descrambler, and the rpyraia of the desc 11 rtr {a group of control outputs of the device, the mHKJpoKOMaHA code) is connected to the MHKJpoKOMaHA register the group of inputs of the decoder, the group of outputs and doses of the code of the software e in x logical conditions: VIY register of micro-commands is connected; with a group of control inputs; a logical conditions multiplexer, the group of information inputs of which is represented by a group of inputs of logical conditions of the device, the first sync input (device animation is connected to the micro-register register synchronization input, the group of information inputs of which is connected to the group of micro-commands memory output and the address information input group, the counting input of which is connected to the output of the multiplexer logical conditions, the third input is synchronous. E tt: t--.

Description

the group of inputs of the logical conditions of the device, the first synchronization input of the device is connected to the synchronization input of the micro-register register, the group of information inputs of which is connected to the group of outputs of the micro-instruction memory block and the group of information inputs of the address register, the installation inputs in U and the synchronization are connected correspondingly with the initial start-up input of the device and with the second synchronization input of the device, characterized in that, in order to reduce the equipment, it contains an adder, and the input is lower a row of the first group of the adder is connected to the multiplexer output of logical conditions, the remaining inputs of the first group of the adder are connected to the zero potential bus, the high-level input of the second group of the adder is connected to the gate input of the multiplexer and the other inputs of the second GROUP of the adder are connected to by the registers of the address register, the group of outputs of the adder is connected to the group of address inputs of the microcommand memory block.

The invention relates to digital computing for building various programmable controllable devices. The purpose of the invention is to reduce the amount of equipment due to more efficient use of the volume of the microinstructions memory block. FIG. 1 shows a block diagram of the proposed device option; in fig. 2 - the same, the second option; in fig. 3 and 4 are time diagrams of the operation of the device, respectively, in the first and second versions. The microprogrammed control unit contains (fig., T, 2) microinstructor memory block 1, micro-command register 2, address counter 3, trigger 4 logic conditions multiplexer 5, decoder 6, initial start input 7, first 8, second 9 and third 10 synchronization inputs, a group of 11 inputs of logical conditions and a group of 12 outputs, an address register 13 and an adder 14. The microprogram control device in the first embodiment is operated as follows. The memory unit 1 in the proposed device is divided into two equal parts, in one of which the operating rooms are encoded, and in the second, the address parts of the microprograms of microprograms. The relative position of these parts depends on the initial state of the trigger 4; in the zero initial state of trigger 4 and the information input connected with zero, the operating parts are coded in the upper part of the memory, and the address parts of microcommands are encoded in the lower part; with a single initial state of trigger 4 and the connection of input D with a single lo. level is the opposite. By a start-up signal (LB), the address counter 3 and the trigger 4 are set to the zero state. The output state of the counter 3 and the trigger 4 is, in this case, the address at which the zero line of the memory block 1 is selected, where the operational part of the first microcommand of microprogrammbi is encoded. At the same time on the input 8 of the device (at the input of the S. Registrar 2 micro-commands) the synchronization signal SI1 arrives with a certain period. The required number of strobe signals and the order in which they arrive are determined, for example, by a synchronization device that is not part of the device. The change of microinstructions (its operational part) in the device occurs at the first strobe signal SI1 (at the input 8. of the device). The execution of micro-commands occurs in the period between the changes of micro-commands (from one SI1 to the next). After recording the transient state of memory block 1 via gate SI1 into register 2 microcommands, microcoding codes are sent to decoder 6, and condition codes (if present in the operating part of the microcommand being executed) are sent to the address input of multiplexer 5. When the initial signal is removed start from rokhod 7 and the receipt of the second signal of cI2 (on input 9 of the device is set up) the following operations occur. Firstly, if the microcommand is conditional (tv; input A of multiplexer 5 has a signal) and input 11 receives the condition corresponding to the code de multiplexer 5 is formed by a signal, gated cm2. This signal is received at the input +1. counter 3, increases the content of the latter by one. At the same time, the trigger 4 is established by the signal CI2 in a single state. In this case, the address input of memory block 1 receives a code, the most significant bit of which is the output state of flip-flop 4, and the remaining bits are output of the counter 3 state of the address, the code at the input of memory V is / address is address the part of the following microcommand, i.e. it is the address of the ruler in which the address of the operating part of the next microcommand is encoded, and at the output of memory block 1, the investigator will set the address of the operational part of the next microcommand. Secondly, if the microcommand was not conditional (there is no condition code at the input of the multiplexer) or the condition is not fulfilled (at the inputs of 11 conditions there is no condition), then at the multiplex output. ra 5 (therefore, at the input +1 of the counter 3) there is a zero signal. As a result, the contents (output state) of the counter 3 os. remains unchanged, and the output state of the trigger 4 is reversed (according to the signal CI2 aa input S of the trigger 4). Consequently, the address will be sent to the address in the :: od of block 1 of the memory, the older bit of the bit has changed, and the lower bits remained unchanged compared to the address of the microcommand to be executed. In addition, the output of memory block 1 in this case will determine the address of the operating part of the micro- command following the execution. When the third strobe signal of the PPE arrives (third strobe) at the inputs 10 of the device (inputs C of the counter 3 addresses and trigger 4) c. the output of memory block 1, the address of the operating part of the following microcommand is written to counter 3, while trigger 4 is set to the initial zero state, since O is set at the information input of the trigger (for a detailed device variant). The PPE signal has a duration significantly shorter than the speed of the memory 1, which ensures that the address of the operating part of the next (new) microcommand is read into counter 3. on signal. PPE before the appearance of block 1 of the operational part of this new microcommand at its address. Thus, at the input of block 1, the address of the operational part of the next micro-instruction is set, i.e. the address of the ruler in which the operative part of the following microcommand is encoded. At the same time, at the output of block 1 there is an operational part of this next microcommand, which is rewritten into register 2 of microcommands when the next sitel of SI1 appears at the input 8 of the device. The cycle for selecting the address of the next (after the executed) micro-command is repeated. The device (figure 2) works as follows. According to the initial start-up signal of the device, which enters the input of the setting O of the register 13 of the address, the last one is set to the initial zero state, which is the address of the operating part of the icommand executed first. This address passes through the adder 14 without changing to the input of the memory 1, causing the output of the last operating part of the microcommand performed by the first, oh, i.e. at the indicated address, from the operational part of the memory volume, a ruler is selected, in which the operating part of the microcommand that is executed first is encoded. Since simultaneously with the initial start signal, the first synchronization signal SI1, which allows writing to it, arrives at the input of the register entry 2 microcommands, the output state of memory block 1 (the operative part of the first microcommand) will be written into register 2 microacamps and using the decoder 6 The incoming control devices of the device 12 (the signal SI1 is fed to the input of the register entry 2 microcommands from the outside for the entire time of the initial start signal at the input of the installation in the register 13 About the address of the frequency of the trace C11 is determined by the frequency c edovani clock, e.g., clock cycles generator device without entering the composition of the device) -. After the initial start signal is removed from device 7 input, the SI signal appears at its input to, which is sent to the high bit of group B of the information inputs of sum mator 14 to the strobing input of the typelexer 5 logical conditions. The signal to input 10 comes from the outside, for example, from the setpoint of the synchronization node, after the first synchronizing signal SI1 has gone (Fig. 4). As a result, the output of the adder 14, and therefore a new address different from the address, will be set on the input of the memory unit 1. the operating part (the initial zero state of the address register .13) of the microcommand executed by the first one, the state of the highest bit. According to the ajatpecy obtained in this way, which is the address of the address part of the next command, the corresponding ruler is selected from the address part of the memory volume, in which the address of the operating part of the next microcommand is encoded, i.e. next microcommand. 0 On the leading edge of the second synchronization signal SI2 at the input 9 of the device and the presence of a signal at the control input 10 of the device, the address of the operating part of the next microcommand from the output of block 1 is written to the address register 13. This address through the adder 14 acts on the input of block 1, in which at this address the corresponding ruler is selected from the operating part of the memory volume, in which the operational part of the next microcommand is encoded and at the output of memory 1 of the control output unit | The operating part of the next microcommand is inserted into / 1, which, with the appearance of the leading edge of the SI signal at the input of the record of register 2, will be recorded into it and through the decoder 6 will go to the control outputs of the device. To select each of the following microcommands from the memory block, the cycle of forming the necessary control actions on the input of the memory block 1 is repeated as described. Moreover, if the microcommand is conditional (there is a signal at input A of multiplexer 5) and the condition is present at the input of the multiplexer, then with the input of the device input 10, at the output of multiplexer 5, and therefore at the inputs of the first group of inputs of the adder Wits signal equal in duration to the signal at input 10. As a result, the Oner address of the radial part of the executed microcommand arriving at the second group of inputs cyj aTopa will add one in the latter, and at the output of the adder we will get the address of the address part of the trace microcommand, which is fed to the input of memory block 1. At the same time, in the address part of the memory block 1, the address of the ruler in which the address of the operational part of the next micro-instruction is encoded is selected at this address. Next, the actions take place according to the described algorithm of the device operation (Fig. 2)

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Claims (2)

1. A microprogram control device containing a memory block of microcommands, ^ a register of microcommands, an address counter, a multiplexer of logical conditions and a decoder, the output group of the decoder being the group of control outputs of the device, the group of outputs of the microoperation code of the micro register register is connected to the group.; of the decoder inputs, the group of outputs of the code of verified logical conditions of the register The microcommands are connected to the group of control inputs of the mule: the logic conditioner, the group of information inputs of which is a group of inputs of the logical conditions of the device, the first synchronization input of the device is connected to the synchronization input of the register of microcommands, the group of information inputs of which connected to the group of outputs of the micro-memory memory block and to the group of information inputs of the address counter, the counting input of which is connected to the output the logic condition multiplexer house, the third input of the device synchronization is connected to the address counter recording input, the installation input to which is the initial start-up of the device, the group of information outputs of the address counter is connected to the group of low-order inputs of the address of the micro-memory block, which differs in that , in order to reduce equipment., it contains a trigger, the output of which is connected to the input of the high-order bit of the address of the memory block of microcommands, the input of the installation in О of the trigger is connected to the input of the initial start-up devices, the information input and the trigger synchronization input are connected respectively to the zero potential bus and to the third device synchronization input, the installation input to the 1 '* trigger and the gate input of the multiplexer, logical conditions are connected to the second device synchronization input. 2. A microprogram control device containing a micro-memory memory block, a micro-instruction register, an address register, a logical condition multiplexer and a decoder, the decoder output group being the device control output group, the micro-register micro-command output group of micro-operation code outputs connected to the decoder input group, and the group of checked logic logic outputs conditions of the micro command register is connected to the group of control inputs of the logic condition multiplexer, the group of information inputs of which is I (N) J159020 by the group of inputs of the logical conditions of the device, the first synchronization input of the device is connected to the synchronization input of the micro-command register, the group of information inputs of which is connected to the group of outputs of the micro-memory memory block and to the group of information inputs. address register, installation inputs at 0 and synchronization which is connected respectively with the input of the initial start-up of the device and with the second input of the synchronization of the device, characterized in that, in order to reduce equipment, it contains an adder, the input being young the last bit of the first adder group is connected to the output of the logical condition multiplexer, the remaining inputs of the first adder group are connected to the zero potential bus, the input of the highest bit of the second adder group is connected to the gate input of the multiplexer and is the third synchronization input of the device, the remaining inputs of the second adder group are connected to the register outputs , pa addresses, the group of outputs of the adder is connected to the group of address inputs of the memory block microcommands.