SU1302277A1 - Microprogram device for priority servicing of subscriber group - Google Patents

Abstract

The invention relates to the field of computer technology and can be used in the construction of monitoring and control devices that process information from a group of subscribers (mode sensors, built-in monitoring tools and other sources). The purpose of the invention is to improve speed. The device contains blocks of permanent and random access memory 1, 2, block 3 forming the address, block 4 forms (L

Description

stack addresses, the first and second registers of the address of the number 7, 8, the first and second registers of micro-operations 9, 10, the register of the address of micro-instructions 11, the first to the third registers of reception for wok 12-14, from the first to the third registers of storage for wok 15 -17, encoder 18, first and second switches 19-21, first to fourth blocks of priority 23-26, first and second decoders 28, 29, first and second

one

The invention relates to computing and to be used in the construction of monitoring and control devices that process information from a group (subscribers) (mode sensors, built-in monitoring tools and other sources).

The purpose of the invention is to increase speed.

Figure 1 shows the functional diagram of the proposed device; Fig. 2 shows a block for forming the address of micro-instructions; FIG. 3 shows a stack address generation unit; figure 4 - the first synchronization unit; on fig.Z - the second synchronization unit; figure 6 - diagram of the data switch.

The device contains blocks of constant 1 and random-access memory 2, block 3 of the formation of the address of micro-instructions, block

4forming stack addresses, first

5 and the second 6 blocks of synchronization, the first 7 and second 8 registers of the address numbers, the first 9 and second 10 registers - register 11 addresses of micro-instructions, from the first to the third reception registers 12-14

and storage 15-17 for the wok, encoder 18, switches 9-22, from the first 23 to the fourth 26 priority blocks, the third key 27 with a three-stable state, the first 28 and second 29 decoders, the first 30 and second 31 keys with a three-stable state by the first, 32–4, the first 35 blocks of the AND elements, the multiplexer 36, the blocking trigger 37, the fifth element AND 38, the third 39 and the fourth 40 AND elements, the second 41 through the fourth 43 OR elements, the data bus 44, the bus 45 conditions

keys with a three-stable state 30, 31, first to fourth blocks of elements AND 32, 35, multiplexer 36, lock trigger 37, elements AND 38-40, elements OR 41-43. The goal is achieved by increasing the hardware to implement a three-level priority service for a group of subscribers with the possibility of interrupting the processing of lower priority applications. 6 ill., 1 tab.

The micro-command address generation unit contains the first element AND 46, the first element OR 47, the first 48 and the second 49 switches, the third decoder 50, the 1K flip-flop 51, the element OR-NOT 52.

The block of formation of the stack addresses contains the fifth 53 and sixth 54 elements AND, the fifth 55 and sixth 56 elements OR, the element 2И-OR 57, the trigger 58 condition, the counter 59.

The first synchronization unit contains the first trigger 60 of the rod, the first generator 61 of pulses, the second element AND 62. The second synchronization unit contains the second trigger 63 of the start, the second generator of 64 pulses, the seventh element AND 65, the seventh 66 and the eighth 67 elements OR.

The data switch contains the element NOT 68, the first 69 and the second 70 keys.

The firmware for servicing the subscriber group operates as follows.

In the initial state, all the registers triggers and the counter 59 are reset. Before starting operation of the device, the first synchronization unit 5 is turned on with a signal on the device start input, after which a series of synchronization signals are formed at the outputs of the first synchronization unit 5.

Upon receipt of a request from subscribers for their service by executing the required sequence of corresponding micro-operations at the outputs of the device, they are stored in registers 12–14 of the request. Vkki in the device come to the inputs

receiving subscribers' bids at times coinciding with the generation of a signal at the second output of the first generator 61. Since the blocking trigger 37 is off, the start1 of the received bids by priority at the time of the sync signal generation will be overwritten in one of the registers of the bid the first output of the first block 5. synchronization

At the moment of rewriting the application into one of the storage registers 15-17, at the output of the element OR-KE 52 a differential signal is generated from a high level to a low one, by which control trigger 51 is activated. At the output of the encoder 18, a code is generated for the initial address of the service firmware for this application, which is transmitted to the information input of the register 11 of the microcommand address.

The signal at the second output of the first synchronization unit 5 turns on the trigger 37 for blocking the second to fourth 33-35 blocks of elements I, triggers the second synchronization unit 6 and writes the address of the initial microcommand to the output of the second synchronization unit 6 - programs in register 11 addresses of microinstructions.

.-

On a signal at the third output of the first synchronization unit 5, the control trigger 51 is zeroed out and the application received in one of the registers 15-17 is serviced from one of the registers 12-14.

Since during the formation of the signals at the first three outputs of the second generator 64 there is no signal at the output of the seventh element OR 66 (at the input of the lower bit of the address of the BPI memory block), the contents of the even cell of the pair indicated by the state of the register 11 the address of the microinstructions, and on the clock signal at the first output of the second synchronization unit 6, it is recorded in the first register 9 of the microoperations. The device begins to form micro-operations at its output.

In the second phase of operation of the second synchronization block 6 (the moments of signal generation at the outputs from the second to the sixth second generator 64), the odd cell of the pair in the PPU 1 is addressed.

fO

15 20

30 25

35

40

45

50

Runs of PPP 1 are distributed and used as follows.

The contents of the micro-ops field is fed to the information input of the register 10, which is stored at the time of generating the signal at the fifth output of the second generator 64. The sodder-pressing field of the micro-instructions address from the output of the control unit 1 is fed to the information input of the 11-register of the micro-instructions, which is stored at the moment forming the signal at the sixth output of the second generator 64. The contents of the BOP 2 address field from the output of the BNP address field are fed through the first switch 19 of the address to the information inputs of registers 7 and 8 for senior and lower bits address and written into them at the time of forming the signal at the fourth output of the second oscillator 64, if generated microoperations microinstruction output at the thirteenth floor control register 9. If algorithm execution firmware interrupt service requires vschachi on the data bus 44 the contents of field constants PPO 1 then generated. micro-operation at the tenth output of register 9, in which the constant is fed to the output of switch 21,

With the issuance of a new series of sync signals at the output of the second synchronization unit 6, the operation of the device for high-level micro-operations at the device output is repeated only with the difference that the addresses of the next microcommands to the register 11 of the microcommands address come from the BPP address field, and not from the output of the encoder 18. If, during the execution of the firmware, it requires recording information from the device data input to the BOP 2 or outputting the content to the BOP 2 at the device data output at the addresses specified by the external subscriber at the data input (or condition input) the devices then develop the corresponding micro-operations that control the operation of the first address switch 19, the data switch 20 and the keys 30 and 31 with a three-stable output, as well as the access and write micro-operations for the BOP 2.

When executing linear microprogram sections, the operation of the device (in developing appropriate microoperations at the output of the field to control the work of subscribers and the device itself) occurs in a similar way.

described during the entire linear portion of the firmware.

The organization of conditional transitions during the execution of microprograms (the branch fragments of the microprograms used are as follows.

The address of the next microcommand modified by the logical conditions supplied to the input of the device conditions, p & is located in the field of the BOT 1 constants read at its output. The arsh part of the address is transmitted to the information input of the register of the 1I microcommand addresses without change, and instead of the lower part of the address of the next microcommand, a code is output from the output of the first priority block 23, which prioritizes the logical conditions received at its input through the first key with the three-stable output 30 and the bus 45 conditions.

Thus, the priority of processing logical conditions is established, which are removed by external devices as they are serviced. After eliminating all logical conditions, when the address of the next microcommand is transmitted from the output of the EPP 1 constant field, the address 11 will receive the address of the microinstructions. The bit corresponding to the output of the first priority block 23.

35

This address corresponds to the microcommand for exiting a branch of a microprogram fragment and passing to its linear portion.

At the end of the service firmware of the corresponding application, a microcommand with microoperations is executed - Q at the outputs 14 and 15 of the control field of the register 9, through which the operation of the second synchronization unit 6 stops and is set to its original state

30 combo with a higher priority, the device operates as follows. When a request arrives at the reception register 12 in the process of servicing the application that arrives at register reception 1 (14.), the interruption resolution is formed by the element 2I-OR. 57 (FIG. 3) in the presence of a micro-operation at the eighteenth exit of the control field of the first micro-command register.

When servicing a request that arrives in the reception register 14 of the request, it is possible to interrupt the firmware of their servicing by applications that have reappeared in the same register 14 (for blocking trigger 37 and re-, "g" -

. . The exclusion of the application memorized in the storage sags 15-17. In addition, the device, at the end of the execution of the microprogram, stops the delivery of micro-operations to the output of the device.

50

switching over, the low-order low register reg 14), if a microoperation is produced at the seventeenth output of the control field of the register 9. In this case, the element 2И-OR 57 will also generate a signal 50

switching on, the low-order low register reg 14), if a microoperation is produced at the seventeenth output of the control field of the register 9. In this case, the element 2I-OR 57 will also generate an interrupt signal,

The interruption of the execution of current microprograms can be carried out.

When servicing the requests of subscribers requiring the execution of a sequence of microprograms (macro programs) at the end of the next microprogram (from first to last), only on its linear sections, when the fourteenth operation and the next microinstruction at the next outputs, the register 9 field is not given At the output of the address field, the microparameter is created, therefore the trigger 37 of the PPO 1 commands and when the constants field is not used in this micro lock and register 15-17

the order is not reset and the second synchronization unit 6 does not stop. In this case, the output of the control of the address of the register 10 is generated

a code that provides the information input of the register 11 with the micro-command address of the initial microprogram address from the output of the first switch of the block 3.

In this case, the initial address of the firmware is formed by the subscriber from two parts: the operation code is formed at the input of the operation code of unit 3, and the number of the serviced device is inputted at the first conditions input of the first switch of unit 3. After that, the next firmware runs in the usual way.

At the end of the last firmware (macro), the second synchronization unit 6 is stopped and the lock trigger 37 and the storage registers 15-17 are reset to the initial state.

In the event of a situation requiring interruption of the fulfillment of the servicing firmware of the quota when the quotation arrives from (groups) subscribers with a higher priority, the device operates as follows. When a request arrives at the reception register 12 in the process of servicing the application that arrives at register 13 (14.) of receiving the request, the interrupt resolution is formed by element 2I-OR. 57 (FIG. 3) in the presence of a micro-operation at the eighteenth exit of the control field of the first micro-command register.

When servicing the application entered into the reception register 14 of the application, it is possible to interrupt the firmware of their servicing by reloading the station, "g" -

“The inclusion of the application memorized in ca50

if the microoperation is produced at the seventeenth output of the control field of the register 9. In this case, the element 2И-OR 57 will also generate a signal on its linear segments only, when the address of the next microcommand is set at the output of the address field of the microprocessor PPP 1 and when the constant field is not used in this microcommand

jerking

The interruption of the current firmware can be done

only on its linear sections, when the address of the next microcommand is given at the output of the address field of the microcommand of PPO 1 and when the field of constants is not used in this microcommand.

in PPP I. In microprograms of microprograms, in which the resolution of interception of microtragrams is set at the seventeenth and eighteenth outputs of the control register 9, all microoperations are generated on the fourth, sixth, seventh, ninth and tenth outputs of the control register 9, which ( irrespective of Toi o, there is an interruption of the firmware, or not) the address of the next world command is stored in the BOP 2 stack at the address indicated by the counter 59, Since the increase in the content of the counter 59 occurs only when the interrupt ii microprograms the last address of the microinstruction stored in the BOP stack 2 before the contents of counter 59 will change

the true return address to the interrupted firmware.

If, when checking for the presence of micro-operations on the eighteenth (seventeenth) output of the control register field 9 of the device, it turned out that the interruption occurs, then the trigger 58 enabled in this case at the time of the signal at the eighteenth or seventeenth output of the control register 9 increases the value of the counter 59 by one , preparing the device for a possible next interruption.

In the same microinstruction, at the output of the register address control field 10, a code is generated that registers the state of the condition trigger 58 (table). In the absence of an interrupt (the trigger 58 is conditionally off), the information input of the register I1 of the microinstruction addresses is the address of the next micro

the commands will come from the output of the address field of microcommands PPO 1 (a natural continuation of the execution of the firmware). If there is an interrupt, the address of the next micro-command will go to the register 11 of the micro-commands address from the output of the BPP 1 constant field and the transition to the next micro-command will occur, which will generate microoperations on the fourteenth and fifteenth outputs of the control register 9 on which the second synchronization unit 6 will stop and reset trigger

37 blocking and storage registers 15-17.

In this way, the condition of a hit that caused

five

O

five

0

0 one hundred nor

an interrupt, to the register 15 (17) of the storage order and the device is being launched to execute its service firmware.

If an interrupt (interrupt in interrupt) is received during the execution of the service firmware application that interrupted the previous firmware, the described actions are repeated.

The end of the servicing firmware of applications that interrupted the servicing of other applications is not done by stopping the operation of the device (turning off the second synchronization unit 6), but returning to the interrupted firmware as follows.

Before the end of the firmware execution, the analysis of the co-contained counter 59 is performed using the elements AND 46 and OR 47 and the micro-operation signal at the fifth output of the control field of the register 9 (Fig. 2). If there is no signal at the output of the sixth element OR of the stack address generation unit 4 (a sign of the absence of an interrupted and incomplete microprogram), a microcommand is selected that ends the operation of the device as described, otherwise a microcommand is selected that returns to the interrupted microprogram. When executing this microcommand, the contents of counter 59 are reduced by one (produced

five

microinstruction on the nineteenth output of the control register field 9).

I

In the following micro-command, the state of the counter 59 (the output of the OR element 56 of the block 4) is analyzed similarly to the described one and a transition occurs

to one of two microinstructions. Moreover, in one of these micro-commands, the signal at the sixteenth output of the control field of register 9 is not developed (a sign that the number of interrupted and incomplete microprograms is more than one — the signal at the output of the OR element 56 of block 4 is absent) and the trigger 58 is not set to its original the state, and in another microcommand on the sixteenth output of the control field of the register 9, the signal that sets the trigger state 58 to the initial state (the output of the OR element 56 of block 4) is absent, which is a sign that the microprocessor amma, for which the refund is et91

with the last or only circuit in the interrupted firmware.

In addition, microoperations are developed in both these microcommands that ensure that the address of the microcommand of the interrupted microprogram is read from the corresponding stack cell BOP 2 and transmitted through the data switch 20, data bus 44, second key 31 with three-stable output, bus 45 conditions, multiplexer 36 to write in the register 11 addresses of microinstructions.

At the end of the execution of this interrupted microprogram of the 11 gs analogous LIZ state of the counter 59 (element OR 56 output of block 4) as described above, the device stops working.

I

35

40

45

00Exit of the first switch of unit 3

01 Tire exit 45 conditions

10 Output address floor PPO 1

11 Vpsod

second switch block 50

00 Output of the first switch of the block 3 55

01 Tire exit 45 conditions

10 Continuation of the table

five

0

five

0

five

0

- an indifferent state, i.e. state that do not affect the generation of control codes by multiplexer 36 at the output of the third decoder 50 of block 3.

Claims (1)

Invention Formula Firmware device for priority service of a subscriber group containing fixed and main memory blocks, first priority block, first and second address registers, first to third decoders, multiplexer, micro-command address register, first and second micro-commands register, first address switch, first and the second switches, the first and second elements AND, the first element OR, the element NOT, 1K-trigger, the first trigger start, the first pulse generator, and the output of the first field of the address of the fixed memory block is connected to the first information input of the first address switch, the output of which is connected to the information inputs of the first and second address registers, the output of the first address register is connected to the higher bits of the address input of the RAM block, the second information input of the first address switch is connected to the device condition bus, the output field the block of permanent memory is connected to the information inputs of the first and second registers of micro-commands, the outputs of the first field of the external control signals of which are connected respectively to the information the inputs of the first and second decoders, the outputs of which and the outputs of the second fields of the external control signals of the first and second registers of micro-commands are combined and connected to the control output of the device; the output of the local control field of the second register of micro-commands is connected to the control input of the multiplex on the third decoder in the O 1K-flip-flop, the output of the first element I is connected to the second input of the first element OR, differing in that in order to increase speed, it contains from the first to the third reception registers wok, the first to third registers for storing wok, with the second to fourth units priority lane with litter, from the first to the sixth digit - Oh goro through the fourth block of elements AND, l local control of the first micro-command register is connected respectively to the control input of the first address switch, the recording input of the first address register, the recording input and the synchronization input of the random access memory block, to the first input of the first element I, to the control input of the second switch, the first information input of the first the switch is connected to the condition bus and to the input of the operation code of the device, the output of the field of constants of the block of permanent memory is connected to the first information input of the first switch and to the first information the multiplexer input, the lower bit of the output of the field of constants of the constant memory block is connected to the first input of the first OR element, the output of which is connected to the low bit of the first information input of the second switch, the output of which is connected to the second information input of the multiplexer, output of the address encoder, trigger blocking, second address switch, second through eighth elements OR, third through eighth elements AND, elements 2I- OR, trigger condition, first through third keys with a three-stable state , bidirectional data switch, constant switch, counter, second pulse generator, second start trigger, element OR NOT, and the first to third inputs of the device are connected to the installation inputs in 1, first to third reception registers, outputs which are connected respectively to the inputs from the second to the fourth priority blocks, the output of the first reception register of the application is connected to the input of the second OR element, the output of which is connected to the first input of element 2И-OR, the output of which is connected to the input of the Set up in 1 trigger condition, the output of the third reception register is connected to the 35th building of the third OR element, the output of the code register of microinstructions, the output of which is connected to the second input of the element which is connected to the address of the address of the 2I-OR, the second output of the first block of permanent memory, the output of the second pulse generator is connected to the first field of whose address is connected to the third information input of the multiplexer, the device condition bus 40 the first input of the first pulse generator is connected to the first input of the first block of elements And the third output of the first pulse generator is connected to the first inputs from the second to four connected to the fourth information input of the multiplexer and to the input of the first priority block, the output of which third input And, the first output of the first pulse generator is connected to the first input of the first block of elements And, the third output of the first pulse generator is connected to the first inputs from the second to the fourth By connecting the second vert an information element blocks and inverse input of the second switch, the output of the 1K-flip-flop is connected to the control input of the first switch, the start-up input of the device is connected to the input the output of the blocking trigger is connected by the second inputs from the second to the fourth blocks of elements And, the outputs of the second priority block are connected to setting the first trigger start to 1; the remaining inputs of the second electric unit, the direct output of which is connected to the start input of the first pulse generator, the stop input of the device is connected to the first input of the second element I, the output of which is connected to the installation input in O of the first trigger trigger, the first output the first pulse generator is connected to the input installation in a 1K-flip-flop, the output of the first element AND is connected to the second input of the first element OR, characterized in that, in order to improve speed, it contains the first to the third reception registers, the first to the third storage registers, second to fourth priority blocks, from pergoro to fourth blocks of AND elements, five 0 five 0 address encoder, blocking trigger, second address switch, second through eighth elements OR, third through eighth elements AND, elements 2И- OR, trigger condition, first to third keys with three-state state, bi-directional data switch, constant switch, counter , the second pulse generator, the second trigger trigger, the OR-NOT element, and the first to the third inputs of the device are connected to the installation inputs in 1, the first to the third registration registers, the outputs of which are connected respectively to the input From the second to the fourth priority blocks, the output of the first receipt register is connected to the input of the second OR element, the output of which is connected to the first input of the 2I-OR element, the output of which is connected to the installation input of 1 trigger condition, the third reception register of the RFQ is connected from the input of the third OR element, the output of which is connected to the second input of the 2I-OR element, the second output of the first pulse generator is connected to the first 35 is the house of the third OR element, the output of which is connected to the second input of the element 2И-OR, the second output of the first pulse generator is connected to the first 40 the primary input of the third element And the first output of the first pulse generator is connected to the first input of the first block of elements And, the third output of the first pulse generator is connected to the first inputs from the second to fourth blocks of elements And, inverse the output of the blocking trigger is connected to the second inputs of the second to fourth blocks of elements And, the outputs of the second priority block are connected to the remaining inputs of the second unit are55 cops And, the output of which is connected to the input of the installation in 1 of the first storage register of the order, the outputs of the third priority block are connected to the remaining inputs of the third block of elements And, the output of which is connected to the input of the installation in 1 of the second register of storage of the wok, outputs of the fourth block 131302277J4 priority is connected to the remaining inputs of the second switch to the inputs of the fourth block of AND elements, the address and the input of the sixth OR element, the output of which is connected to the input of the us output of which is connected to the second input of the third register of the third register, the output of the fourth device is connected to the input of the first ment and connected to the installation inputs of the switch with a three-stage state, in O from the first to the third registers whose output is connected to the storage bus wiring and connected to the third output of the lockout trigger, the address of the block of the constant memory, the outputs of the storage registers of the quotes with the first information input of the first to the third are combined and the sub-switch constants, the output floor is connected to the inputs of the fourth an elemental constant of the constant memory block of the OR connection, to the input) of the address encoder, inna with the second information input. The inputs of the OR element and the rest of the constant switch, whose output to the inputs of the first block of AND elements, you - is connected to the information input of the third - move which connected to the entrances of the three-state key from the first to the third, the output of which is connected to the reception registers, the output of the cipher-bus of the device, the output of the address block connected to the second information memory the first mation input of the first switch, the information input of the switch, the output of the 1K-flip-flop is connected to the second data, the condition bus of the device input of the third element AND output, the output by the second input of the I-ШШ element, from the seventh one is connected to the data bus of the sixth-sixth field device, the information inputs and output of the local control of the first register are connected to the data bus of the micro-commands, the corresponding devices and information input but to the control inputs of the second combo of the second key from the three-stable address rotator, the switch of constants, standing, the output of which is connected to the control inputs from the first tr-bus device conditions, the output of keys from the three-stage OR is NOT connected to the blue input, the first input of the fourth, the seventh synchronization and the I input of the 1K-flip-flop, the eighth and the eighth elements AND, the input of the 1K-flip-flop is connected to the installation bus in the O-flip-flop, and also the zero potential of the device, directly and through the element NOT to 35th input of the third element I, is connected to the control input of the data switch, the installation inputs in 1 trigger the seventeenth discharge field of the local packing and the second trigger start and the first register microcommands as the first input eighth element It is connected to the fourth input of the element-OR, the output of the seventh element AND 2, AND-OR, and to the first input of the fifth one is connected to the installation input of the second OR element, the eighteenth timed start trigger, the output of which is local control of the first relay. -connected to the start-up input of the second gistra of micro-commands connected to the second pulse generator, the first output to the 2I-OR input and connected to the second input to the synchronous input of the first element OR, -generation of the first micro-command register, local field of local control the second the output of the second generator of the first register of micro-commands of the sub-pulses is connected to the first input of the first input of the sixth element of the seventh element OR, with the second input AND, the output of the fifth element OR the connection of the fourth element AND, and the input with the first input of the fifth element AND, you synchronize trigger conditions, the trigger condition trigger is connected to the second input of the second generator by the pulse inputs of the fifth and sixth element-QOB connected to the second input of the sevenths AND with the gate input of the third element OR and the entrance of the synchro desh the informer, the outputs of the torus and the neck of the second register of microinstructions, that of the elements I, are connected to the fourth output of the second generator, which is connected to the second input of the counter, to the second input, to the second input, to the second input the input of the seventh element OR exit the eighth element OR is connected to the synchronization input of the register of microinstruction addresses, the fifth output of the second pulse generator is connected to the fourth input of the seventh OR element, to the second input of the eighth AND element, and to the third inputs of the fifth and sixth And elements, the sixth generator output the pulses are connected to the second input of the seventh element AND, the output of the seventh element OR is connected to the read input of the permanent memory unit, the output of the eighth element AND is connected to the synchronous inputs of the first and second address registers) the output of the first switch is connected to the fifth input of the multiplexer, te.5 Editor A. Shandor Order 1682, Circulation 673 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 IG.V Compiled by A.Soshkin Tehred M. Morgental Proofreader I. Musk