SU1187173A1 - Device for lexical analysing of symbol texts - Google Patents

Abstract

1. DEVICE FOR LEXICAL ANALYSIS OF CHARACTER TEXT, containing two registers, an encoder, the first switch, the first information input of which and the encoder input are connected to the bits of the first register, whose information input is the information input of the device, the encoder's output is connected to the second information input of the switch and with the input of the synchronization unit, the first and second outputs of which are connected respectively to the first and second enabling inputs of the first switch, the third output is connected to the syn roniziruyugdim input of the first register, the outputs of the second register bits are data output devices of tlichayusche ec in that in order to improve performance, it introduced comparing blocks, the memory blocks permutations of texts, text encoder substitution, second and third. switches, substitution control unit, an OR-NOT element and an OR element whose output is connected to the first input of the substitution control unit, the first output of which is connected to the permissive inputs -: comparison blocks and address inputs of the text memory blocks, the output of each comparison block with the corresponding inputs of the OR-NOT element, the coded text of the substitution text, and with the first input of the read resolution of the corresponding memory block of the text of substitutions, the second input of the read permission of which is connected to t The output of the synchronization block, the output of the OR element is NOT connected to the second input of the control unit of the stand (Line, the third input of which is connected to the third output of the synchronization block, c: output outputs of the text memory blocks of substitutions are connected to the inputs of the OR element, information outputs connected respectively to the information inputs of the second switch, the enabling input 00 of which is connected to the output of the encoder text of the substitution text, the output is connected to the first information input of the third to The switching unit information inputs and the second information input of the third switch are connected to the output of the first switch, the synchronization inputs of the comparison blocks are connected to the second output of the substitution control unit, the third and fourth outputs of which are connected to the third input of the third switch, respectively. register, the fifth output is connected to the input of the first register write lock and to the third permitting input

Description

I will give you the memory of the text memory blocks of substitutions, the output of the switch is connected to the information input of the second register, the fourth, fifth,. The sixth and seventh outputs of the sync block are connected respectively to the fourth, fifth, sixth and seventh inputs of the substitution control block, which contains two flip-flops, four AND elements, an ORI-NOT element, the output of the first And element, and are connected to the single inputs of the first and second triggers and with the first output of the substitution control unit, the first and second inputs of which are connected respectively to the first zero input of the second trigger with the first input of the second element I, the third input is connected to the first inputs of the third element This AND of the I-VDI-NOT element whose second input is the fourth input of the substitution control unit, the fifth and sixth inputs of which is the first BTopr iM input and the first AND element, respectively, the seventh input is the zero input of the first trigger, the output of which is connected to the second input of the third element AND, the output of which is the second output of the substitution control unit, the third output of which and the first input of the fourth element I are connected to the single output of the second trigger, zero output of which is third the input of the AND-OR element is NOT, the fourth input of which and the fifth output of the substitution control unit are connected to the output of the fourth element AND, the second inputs of the second and fourth fourth elements AND are connected to the zero output of the first trigger, the output of the second element 3 is connected to the second zero input of the second flip-flop, the output of the I-NI-N-element is the fourth output of the substitution control unit. 2, - The device according to claim 1, wherein the synchronization unit comprises a decoder, three flip-flops, four AND elements, an OR element, and a clock generator, the output of which is connected to the sync input of the first trigger, the first inputs of the first and second elements And with the third output of the block, the input of the decoder is the input of the block, the first output of the decoder is connected to the first input of the third And element, the second output is connected to the single input of the second trigger and the seventh output of the decoderconnected to the zero and single inputs of the third trigger, the fifth output is the fifth output of the block, the zero output of the third trigger is connected to the second input of the third And element, and to the sixth output of the block, the third input of the And, to the second input of the first element And, to the zero input of the second trigger and the first output of the block, the outputs of the first and second elements AND are connected respectively to the inputs of the OR element, the output of the Second is the fourth output of the block, the single output of the second trigger is connected to the Nome input of the first flip-flop and to a first input of the fourth AND element, -second input coupled to the zero output of the first flip-flop, the fourth output element and connected to the second input of the second AND gate and a second output unit.

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The invention relates to computing and can be used for the analysis of symbolic texts in dancers from programming and microprogramming languages, in text editing systems.

The purpose of the invention is to increase speed by reducing the amount of information by autogenerating repeated fragments of symbolic text.

Figure 1 shows the structural diagram of the attached device} in figure 2 - block diagram of the synchronization unit; FIG. 3 is a switch diagram; figure 4 - structural diagram

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the switch 11. The control input of the switch 11 from the output of block 6 receives a zero signal, since the trigger 28 is in the zero state (this is its initial state). When the signal at the control input is zero, the switch 11 sends information to its output from the second information input, the binary code of the information symbol is written to register 2 when the next pulse arrives at its sync input

The formation of the sync pulse in the register 2 in this mode is carried out as follows. Pulses from the output of the generator 23 clock pulses (FIG. 8, a) are received through the element AND 20 (figure 2) and the element OR 22 at the output of the synchronization unit 4, since the output of the first element AND 16 in this mode contains a single signal. Further, these pulses arrive at the input of the I-IPI HE 33 element in the biped block of the inverted form and arrive at the output of block 6 and then to the synchronizing input of the register 2, because at the input of the H-OR-HE element 33 there is a resolving single signal from the zero output of the trigger 28 .

If the next character is a separator, then a single signal from the second output of the decoder 14 (Fig. 2) sets the trigger 17 to the one state. The trigger 18 in the initial state is in the zero state, therefore, from its zero output, the input signal of the element 19 is supplied with a single signal. As there is a single signal from trigger 17 at the other input of AND 19, a single signal is formed at the output of AND 19. This control output signal of the synchronization unit 4 is fed to the input of switch 5 and provides transmission from the output of the encoder 3 corresponding to the internal separator . Just as in the first mode, this code goes through switch -11 to the information input of register 2. The control signal from the output of the AND 19 element also goes to the second input of the AND 21 element, ensuring the passage of the next pulse through it, which passes through described for the first mode of the circuit and enters the synchronization input of register 2. When

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This records the internal separator code in register 2. If the first character of the separator is also followed by separator characters, their recording in register 2 will be blocked, because when the next pulse arrives at the input of the trigger 18, it goes into one state. In this case, a zero signal is generated at the output of the element 19, which blocks the transmission of the internal separator code through the switch 5 and prohibits the supply of pulses to the synchronization input of register 2. Both flip-flops 17 and 18 are reset to the initial state when the information symbol arrives.

If the input character defines the beginning of a comment, then a single signal is generated only on the third output of the decoder 14, setting trigger 15 to one state. The zero signal from the zero output of the trigger 15 locks the element AND 16, as a result of which the operation of the switch 5 and the element 16 is blocked. Therefore, if further information characters enter the input of the device that is in the comment mode, they will not be transmitted for recording register 2 and its state does not change. The device exits comment mode when a fourth group character arrives at the end of a comment. In this case, the trigger 15 comments is transferred to the initial zero state.

If the input symbol is a keyword marker, then a single signal is generated only at the fifth output of the decoder 14, and the device is switched to the substitution mode. The marker code in register 2 is not recorded, since its transmission through switch 5 is blocked by a zero signal from the output of element 16, when the trigger 15 is in the zero state, a single signal is generated at the output of element 29 when the marker enters (FIG. 1, c), according to which the triggers 27 and 28 are transferred to a single state (fig.8, g, k), the memory nodes 34 and 39 of all blocks 7 and 8. are set to the initial state. A single signal from a single output of the trigger 27 provides for the issuance of clock pulses to the second output of the substitution control unit 6 via

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the sixth element AND 30 (Fig. 8, d) for checking the matching of the characters of the input keyword with the symbols of the reference words stored in the memory nodes 34. When j 1 comes into the register 1 register of information symbols that constitute the input kgioch word, they pass through the switch 5, since the output of element 16 when reading the characters of the first group of group 1 does not have a single enabling signal. The code of the next character of the input keyword simultaneously arrives at the input of the comparison circuit 35 of each of the blocks 7 of keyword verification. All blocks 7 operate in parallel, since each of them receives control signals from substitution control blocks 6.

Consider the operation of one of the blocks 7. After the initial installation signal arrives at the input of the memory node 34, its address counter 44 is reset to the initial zero state, and the first symbol of the reference keyword, which is input to the 35 (figure 5). If the codes at the inputs of the circuit 35 coincide, then a single 30 signal is generated at its output (Fig. 8e). In this case, when the first clock pulse arrives at the input of the trigger 37, it is set to one (Fig. 8,). Its passage: through the element And 38, 35 provides the resolution signal from the single output of the first trigger 36, which is set to one by the signal from the output of the element And 29 of block 6 (Fig. 8, g). If - all 40 characters of the input keyword coincide with the symbols of the reference word, then at the end of the test, the trigger 37 will remain in the one state. If at least one of the symbols does not coincide with the 45 reference, then the trigger 37 on the zero signal from the output of the element 38 will be reset to the zero state. A single signal from the zero output of the trigger 37 will reset the trigger 36 to zero. As a result, this element 38 will be further locked and the trigger 37 will remain in the zero state, even if the following characters of the input string, the string word match the symbol - 55 wars-1 and reference words.

Since each of the blocks 7 stores different reference key layers 7310

on, then the enabling signal indicating the complete match of the input keyword with the reference one will only be present at the output of one of the blocks 7 at the end of the test. The end of the input keyword occurs when the next character read from Exit register 1 turns out to be a separator. A single signal from the second output of the decoder 14 is fed to the input of the trigger 27 in block 6 and puts it in the zero state (FIG. 8, d). This completes the verification phase of the keyword. At this stage, the input characters of the keyword were read from register 1, but they were not written to register 2, since both AND elements included in the AND-OR-NOT 33 element were locked with zero signals from the AND 31 output of the element (FIG. .8, l) and from the zero output of the trigger 28. In the second stage, in the substitution mode, a single signal from the output of the element I 31 ensures the passage of clock pulses through the I-IPI-HE element 33 (FIG. 8, m) to the clock input of register 2, except In addition, this control signal provides the permission to read the texts of the ov from blocks 8 and at the same time blocks the entry in register 1 of new characters in the input character string.,.

The permissive signal from the output of block 6 is fed to the input of the element And 42 in the cleansing block 8. Another allowing signal, generated at the output of only one block 7, is fed to the input-element of And 42 only in block 8. As a result, the clock pulses through the element And 42 only in one block 8 and will provide the reading of the selected .txt of the substitution from its memory node 39. The readable substitution text is character-driven from the information output of the corresponding block 8 to the information input of the switch 10 of the same name. The encoder 9 generates the binary code of the block number 8, this code goes to the control input of the switch 10 and provides a connection to the output of the switch 10 of its corresponding information input. As a result, the characters of the selected substitution text are alternately fed to the information input of the register 2 for recording into it via the switch 11 of the substitution control unit; Fig. 5 is a block diagram of a comparison block; Fig. 6 is a block diagram of the memory of the substitution text; Fig. 7 is a diagram of the memory node; Figure 8 shows timing charts for the operation of the device. The device contains the registers 1 and the encoder 3, the synchronization unit 4, the switch 5, the substitution control unit 6, the comparison blocks 7, the substitutions text memory blocks 8, the substitution text encoder 9, the switch 10, the switch 11, the element OR NOT 12 the element OR 13, decoder 14, trigger 15, element AND 16, triggers 17 and 18, elements AND 19-21, element OR 22 generator 23 synchronous pulses, groups 24 and 25 elements AND, group 26 elements OR, triggers 27 and 28, elements AND 29-32, AND-OR-HE element 33, 34pam node, comparison circuit 35, triggers 36 and 37, AND 38 element, node. 39 memory, comparison circuit 40, memory constant node 41, AND element 42, register group 43, address 44 counter. The operation of the device is explained by the diagrams shown in Fig. 8, where a is the diagram at the output of the sync pulse generator 23; b - chart at the output of register 1; c - chart at the output of element 29 of the substitution control unit 6; g - diagram on the unit output of the trigger 27; d - diagram at the output of the element And 30; e is the output diagram of the comparison circuit 35; W - diagram at the output of the trigger 36; and - diagram on the unit output of the trigger 37; to chart on the unit output of the trigger 28; l - diagram at the output of the element And 31; m - diagram at the output of the element AND-OR-NOT 33; n output diagram of comparison circuit 40; p - chart at the output of the register 2. Register 1 is intended for storing the BINARY code of the next analyzed character from the input character string. Input for register for 1 receives the symbols of the source text (programs, user firmware) for example, from a buffer memory (not shown). Register 2 is intended to store the next character of the output compressed text containing only dexemes (character sequences. 73 -. 4 meaningful for a specific microprogramming language), separated from each other by the characters of the spruce oil. And the output text may contain newly substituted leximes or a sequence of them instead of the highlighted source text keywords. The encoder 3 is designed to generate a control code by the code of the next character of the input text to control the grammatical parsing of the input character text in order to identify the meaningful structures of the microprogramming language. The synchronization block 4 is designed to generate control signals using the control code from the encoder 3, allowing either skipping the character from register 1 to registry 2, writing the internal separator character code from the output of encoder 3 to register 2, or ignoring the sequence of input characters of their register 1, or substituting, instead of a group of input signals from register 1, defined as a keyword, a predetermined sequence of characters recorded from the output of one of blocks 8, register 2. Switch 5 is preset VALUE for transmitting at its output one of two binary codes, the information present at its inputs, depending on the presence of an enable signal on one of its two steering inputs. The substitution control unit 6 is designed to generate control signals when the synchronization unit develops a control signal that allocates the beginning of a keyword in order to compare it with the reference keywords and, in case the input keyword coincides with one of them, it is replaced in advance certain character, text. Each of the blocks 7 is designed to generate a control signal in the event that the input keyword matches the corresponding reference word stored in the block. . Each block 8 is designed to issue the corresponding (predetermined and stored in it) text of substitution into register 2 in case the input keyword matches the reference stored in the same block 7. The encoder 9 is designed to form the binary code of that key block words, at the output of which a single signal is generated that the received keyword matches one of the reference ones. Such a signal can always be generated only at the output of one of the blocks 7. Therefore, the encoder 9 actually both bakes the conversion of the unitary code at its output into the binary code at its output. Switch 10 is designed to transfer to its output the characters of the text of the substitution from one of its information inputs, depending on the binary code, on its control 101 ((its input. Switch 11, by its functions, is analogous to switch 5 and is intended to transmit to its output the jni6o symbol of the substitution text, or a compressed input text, depending on the value of the signal at its control input. The main task of the lexical analysis device is to transform the original character text to highlight the meaning x constructions (tokens) from the source character text written in the appropriate programming language (microprogramming) and transmission for further syntax analysis. Simultaneously with this, the device provides a compressed presentation of information in the course of solving this problem, since in the source character text of the program (microprogram ) there is always redundant information in the form of delimiters used in an unlimited number of comments necessary to ensure the readability of microprograms programmer. All E1 redundant information should not arrive at the output of the device, since it will complicate the syntax analysis and significantly increase its time. In addition, when extracting special constructions from the original symbolic text, called keywords, the device is os111; a new symbolic text replacing them into the original text is presented, which is a more detailed semantic structure, with the aim of increasing the efficiency of further syntax analysis of the compressed symbolic text of the source program (firmware). On the rising edge of the sync pulse arriving at the sync input of register 1, in the absence of a single signal at the write lock input, the binary code of the next us wave of the input line is written into register 1 (Fig. 8 b) and comes from its output at the input of the encoder 3. On the control code formed by the encoder 3, the decoder 14 generates a single control signal at its corresponding output, depending on which of the five groups belongs to the next character. When the input symbol belongs to the first group (information symbol), a single signal is generated at the first output of the decoder 14. If the input symbol corresponds to the second group (delimiters), a single signal is generated only at the second output of the decoder 14. The control code corresponding to the input symbol of the third group (the symbol Begin comment), excites the third output of the decoder. . 14, the code corresponding to the fourth group (. Symbol End of the comment) is the fourth output of the decoder 14. The control code. Corresponding to the input symbol of the fifth group (the symbol f.apкep keyword), provides for the formation of a single signal at the fifth output of the decoder 14. Consider successively the device operation mode when processing symbols of each of the five groups. . If the symbol is informational (the first group) and trigger 15 is in the zero state (this means that the text being received for analysis is not a comment), then from the outputs. Yes, register 1, this information symbol comes through switches 5 and 11 and is written to register 2. This is achieved by the fact that at the output of trigger 15 (the initial state of trigger 15 is zero) there is a single signal. A single signal from the output of the element And 16 is fed to the input of the switch 5, which in this case passes the code of the input character from the output of register 1 to the information input

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(figl8, p). In substitution mode. This switch 11 transmits to its output the symbols from the information input, since at its control input there is a single signal generated at the output of block 6, i.e. at the single output trigger 28 (Fig, and). The end of the reading of the substitution of the selected text is determined by the comparison circuit 40. At the end of each substitution text, there is a special end character code.

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text. This code is also stored in the constant memory node 41. When reading the character code of the end of the replacement text from the memory node 39, the comparison circuit 40 at its output generates a match signal (Fig. 8n), which from the output of the block 8. Through the element Sh1I 13 is fed to the input of block 6 and then to the trigger input 28 The trigger 28 returns to the initial zero state, which means the device is finished in the substitution mode.

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Claims (2)

1. DEVICE FOR LEXIC ANALYSIS OF SYMBOL TEXT, containing two registers, an encoder, a first switch, the first information input of which and the input of the encoder are connected to the outputs of the bits of the first register, the information input of which is the information input of the device, the output of the encoder is connected to the second information input of the switch and to the input of the synchronization unit, the first and second outputs of which are connected respectively to the first and second enable inputs of the first switch, the third output is connected to the synchronization uyuschim input of the first register, a second discharge outlets "registers are data output devices of tlichayusche I e with the fact that, in order to increase performance, in comparison blocks has been entered, text memory blocks permutation encoder lookup text, second and third. switches, substitution control unit, OR element and element OR, whose output is connected to the first input of the control unit, the first output of which is connected. nen with the permissive inputs of the comparison blocks and the address inputs of the memory blocks of the substitution text, the output of each comparison block is connected with the corresponding inputs of the IPI-NOT element, the substitution text encoder, and with the first input of the read permission of the corresponding memory block of the substitution texts, the second read permission input which is connected to the third output of the synchronization unit, the output of the OR element is NOT connected to the second input of the substitution control unit, the third input of which is connected to the third output of the sync unit onization, outputs of the end of the output of substitution text memory blocks are connected respectively to the inputs of the OR element, information outputs are connected respectively to the information inputs of the second switch, the permitting input of which is connected to the output of the substitution text encoder, the output is connected to the first information input of the third switch, information inputs of comparison blocks and the second information input of the third switch is connected to the output of the first switch, the synchronizing inputs of the comparison blocks are connected with the second output of the substitution control unit, the third and fourth outputs of which are connected respectively to the decisive decisive input of the third switch and to the synchronizing input of the second register, the fifth output is connected to the write lock input of the first register and to the third enable inputs of reading text memory blocks · substitutions, the output of the switch is connected to the information input of the second register, fourth, fifth,. '· The sixth and seventh outputs of the synchronization unit are connected respectively to the fourth, fifth, sixth and seventh inputs of the substitution control unit, which contains two triggers, four · AND elements, an OR-NOT element, the output of the first AND element is connected to the unit inputs of the first and second triggers and with the first output of the substitution control unit, the first and second inputs of which are connected respectively to the first zero input of the second trigger and to the first input of the second element 'AND, the third input is connected to the first inputs of the third element and AND of the AND-OR-NOT element, the second input of which is the fourth input of the substitution control unit, the fifth and sixth inputs of which are the first and second inputs of the first AND element, respectively, the seventh input is the zero input of the first trigger, the single output of which is connected to the second input the third element And, the output of which is the second output of the substitution control unit, the third output of which and the first input of the fourth element And are connected to the single output of the second trigger, the zero output of which is connected to the input of the AND-OR-NOT element, the fourth input of which and the fifth output of the substitution control unit are connected to the output of the fourth AND element, the second inputs of the second and fourth elements AND are connected to the zero output of the first trigger, the output of the second element And is connected to the second zero input of the second trigger, the output of the AND-OR-NOT element is the fourth output of the substitution control unit. 2, - The device according to claim 1, which entails that the synchronization unit comprises a decoder, three triggers, four AND elements, an OR element, and a clock generator, the output of which is connected to the synchronizing input of the first trigger, with the first inputs of the first and the second elements And and with the third output of the block, the decoder input is the input of the block, the first output of the decoder is connected to the first input of the third element I. “I have the second output connected to the single input of the second trigger and to the seventh output of the block, the third and fourth outputs of the decoder are connected respectively to the zero and single inputs of the third trigger, the fifth output is the fifth output of the block, the zero output of the third trigger is connected to the second input of the third AND element and with the sixth output of the block, the output of the third element And is connected to the second input of the first element And, to the zero input of the second trigger and to the first output of the block, the outputs of the first and second elements And are connected respectively the inputs of the OR element, the output of which is the fourth output of the block, the single output of the second trigger is connected to the installation input of the first trigger and to the first input of the fourth element And, the second input of which is connected to the zero output of the first trigger, the output of the fourth element And is connected to the second input of the second element And and to the second output of the block.