RU2239866C2 - Device for limiting access of users to sections of text documents - Google Patents

Abstract

FIELD: computers.

SUBSTANCE: device has three registers, memory block, synchronizer, two groups of AND elements, a group of Or elements, trigger, AND element, three OR elements and four delay elements. Device also includes selector for sections of text documents, selector of addresses of sections, displacement register, two counters, comparator, two OR elements and AND element. Identification code of user is inputted into first register, and identification code of document section - in second register.

EFFECT: higher reliability.

4 dwg

Description

The invention relates to computer technology, in particular to devices for restricting access to sections of text documents.

Known devices that could be used to solve the problem [1, 2].

The first known device comprises a central processor connected to a logical processing and control unit, the outputs of which are connected to memory blocks connected to the central processor by a common data bus, and an interface unit [1].

A significant drawback of this device is the low reliability of differentiation of access for various users to editable information in sections of the same documents.

Another device is known that contains a central processing unit (CPU), a memory unit, the control inputs of which are connected to the outputs of the CPU, and the outputs are connected to a data processing unit, AND, OR logic elements, and an interface unit [2].

The last of the above technical solutions is closest to the described.

Its disadvantage also lies in the fact that it cannot provide reliable delimitation of user access to various sections of editable text documents. The latter circumstance is due to the fact that the constructive implementation of this device does not provide for fixing user identifiers to those sections of editable text documents that are allocated to the corresponding users for editing.

The purpose of the invention is to increase the reliability of restricting user access to sections of text documents by securing user identifiers to those sections of text documents that are assigned to them for editing.

This goal is achieved by the fact that in the device containing the first register, the information input of which is the first information input of the device, and the synchronizing input is the first synchronizing input of the device, the second register, the information input of which is the second information input of the device, and the synchronizing input is the second synchronizing input device, a memory unit, the information inputs of which are connected to the outputs of the corresponding elements OR groups, the address inputs of the memory unit are connected to the corresponding outputs of the third register, and the outputs of the memory block are connected to one of the inputs of the corresponding elements of the first group, the outputs of which are the information outputs of the device, the second group of elements AND, one of the inputs of which are the information inputs of the device group, and the outputs are connected to the inputs of the corresponding elements of the OR group, a synchronizer, the first and second control inputs of which are the first and second control inputs of the device, a trigger, a single output of which is connected to one input of the first of the And element, the other input of which is connected to the shear output of the synchronizer, the first, second, and third OR elements, the first, second, third, and fourth delay elements, a section for text documents is introduced, the information input of which is connected to the output of the first register, the synchronizing input is connected to the first clock output of the synchronizer, and the control outputs are connected to the inputs of the corresponding elements of the first and second groups, the address selector sections, the information input of which is connected to the output of the second o register, the information output is connected to the information input of the third register, the synchronizing output is connected to the synchronizing input of the third register, the shift register, the information input of which is connected to the information output of the selector of sections of text documents, the synchronizing input is connected to the synchronizing output of the selector of sections of text documents, and the control input connected by a shift to the output of the first element And, the first counter, the counting input of which is connected to the output of the first element And, the output is transferred the wasp of the first counter is connected to one input of the first OR element, the other input of which is connected to the synchronizing output of the selector for text documents, and the output is connected to the input of the first delay element, the second counter, the counting input of which is connected to the transfer output of the first counter, and the output is connected to one the input of the second OR element, the other input of which is connected to the transfer output of the first counter, and the output is connected to the installation input of the trigger, a comparator, the information inputs of which are connected to the outputs of W In the first register and shift register, the clock input is connected to the output of the first delay element, the first output of the comparator is connected to a single input of the trigger, and the second output is connected to the installation input of the second counter, to the third input of the second OR element and to one input of the third OR element, another input which is connected to the second clocking output of the synchronizer, and the output is connected to the synchronizing input of the section address selector, the synchronizing output of which is connected to the input of the second delay element, the output to otorogo connected to the installation input of the shift register, the second element And, one input of which is connected to the first control output of the synchronizer, the other is connected to the output of the second delay element, and the output is connected to the input of the third delay element, with the input control reading the memory block and the corresponding inputs of the elements And of the first group, the third AND element, one input of which is connected to the second control output of the synchronizer, the other is connected to the output of the second delay element, and the output is connected to the control input the memory block and with the input of the fourth delay element, the fourth OR element, the inputs of which are connected to the outputs of the third and fourth delay elements, and the output is connected to the installation inputs of the first, second and third registers, while the first installation input of the synchronizer is connected to the output of the third delay element and the second installation input of the synchronizer is connected to the output of the fourth delay element.

The invention is illustrated by drawings, where Fig. 1 shows a block diagram of a device, Figs. 2 and 3 show examples of a specific embodiment of a text document section selector and section address selector, respectively; Fig. 4 shows an example of a specific synchronizer embodiment.

The device (figure 1) contains the first 1, second 2, third 3 registers, shift register 4, comparator 5, first 6 and second 7 counters, memory unit 8, selector 9 sections of text documents, selector 10 address sections, synchronizer 11, first 12, second 13 and third 14 AND elements, the first 15, 16, 17 and the second 18, 19, 20 groups of AND elements, a group of 21 OR elements, trigger 22, the first 23, the second 24, the third 25, the fourth 26 OR elements, the first 27, second 28, third 29 and fourth 30 delay elements.

1 also shows the first 31 and second 32 information inputs of the device, the first 33 and second 34 clock inputs of the device, the first 35 and second 36 control inputs of the device, group 37, 38, 39 of the information inputs of the device, signal 40 output of the device and group 41 , 42, 43 information outputs of the device.

In addition, the synchronizer 11 contains the first 44 and second 45 installation inputs, a shift output 46, the first 47 and second 48 clock outputs, as well as the first 49 and second 50 control outputs. The selector 9 sections of text documents contains information 51 and synchronizing 52 inputs, controlling 53 outputs, information output 54 and synchronizing 55 outputs, respectively. The section address selector 10 comprises an information input 56, a clock input 57, an information output 58, and a clock output 59.

The selector 9 sections of text documents (figure 2) contains a decoder 60, elements 61-63 And, a memory block 64, made in the form of read-only memory (ROM) and a delay element 65.

The partition address selector 10 (FIG. 3) comprises a decoder 66, elements 67-69 AND, a memory unit 70 made in the form of read-only memory (ROM) and a delay element 71.

The synchronizer 11 (figure 4) contains triggers 72, 73, a pulse generator 74 and elements 75, 76 I. The generator 74 has two outputs. At the first output 46, the generator 74 provides shear pulses with a given frequency, and at the second output, the clock pulses obtained by dividing the frequency of the shear pulses.

All nodes and elements of the device are made on standard potential-pulse elements.

The device operates as follows.

In an information network, a group of users is working on editing various sections of the same document. The fundamental requirement in organizing such work is strict confidentiality, in which each user should have access only to those sections of text documents that he is entrusted with editing. Moreover, access to view other sections of the same document by the specified users should be blocked.

In the process of working in the register 1 from the information input 31 by the clock signal from the input 33 receives the user identification code. In register 2 from the information input 32 on the clock signal from the input 34 receives the code section of a text document with which the user intends to work. Then, through the input 35 of the synchronizer 11 to the single input of the trigger 72 receives a request signal to start work. The trigger 72 with a high potential from a single output opens the element 75 And, through which the first clock pulse of the generator 74 is supplied to the output 47 of the synchronizer 11 and then to the synchronization input 52 of the selector 9.

The decoder 60 of the selector 9 according to the code received at its input 51 from the outputs of the register 1, produces a high potential at one of its outputs and opens one of the elements of I.

For definiteness, we assume that this element is element 61 I. In this case, the pulse from input 52 of selector 9 passes through this element to the read input of the corresponding fixed memory cell in ROM 64 and reads its contents through output 54 to the input of shift register 4. The same pulse delayed by the element 65 at the time of reading, from the output 55 of the selector 9, the read code is entered in register 3.

The contents of a fixed ROM cell is a set of consecutive numbers of sections of a text document, presented in the form of binary decimal codes, access to editing the contents of which is allowed to the user with this identification code. The first of the codes represented in the upper digits of the shift register 4 is fed to one of the inputs of the comparator 5, the other input of which from the output of the register 2 receives the section number code requested for editing and also presented in binary decimal code.

To synchronize the process of comparing codes in the comparator 5, a pulse is used from the output 55 of the selector 9, which passes through the OR element 23, is delayed by the element 27 for the time the code is entered in register 4 and then arrives at the synchronizing input of the comparator 5.

If the codes of register 2 and the upper bits of register 4 are the same, then at the output A of comparator 5 a signal is generated that passes through element 25 OR to input 57 of selector 10.

At this point in time, according to the code from the output of register 2, the decoder 66 of the selector 10 at one of its outputs showed a high potential and opened one of the elements 67-69 I. For definiteness, we assume that this element is element 67 I. In this case, the pulse from the input 57 passes through element 67 And to the input of a fixed cell ROM 70 and reads its contents through output 58 to the input of register 3, where the code is entered by the pulse delayed by element 71 for the duration of reading.

In a fixed cell ROM 70 is stored the address code of the section of the text document, which the user calls for editing. After entering the code of the address of the section in register 4, this code is fed to the address input of the memory unit 8, and the pulse from the output 59 of the selector 10, delayed by element 28 while the code is entered in register 3, is fed, first, to the installation input of the shift register 4 and secondly, through the And element 13, open at the second input with a high potential from the zero output 49 of the trigger 73 of the synchronizer 11, to the read input of the memory unit 8.

From the output of block 8, the contents of the corresponding section of the text document is supplied through the corresponding group of elements 15-17 AND to the user's workstation. Given that in our example, the high potential of the decoder was at the input of the element 61 AND of the selector 9, the transfer of the contents of the section will be carried out through the group of 15 elements AND, also connected to the same output of the decoder 60 of the selector 9. For this purpose, a read pulse is fed to the inputs of the elements 15 And, overwriting the contents of the section of the memory block to output 41.

The cycle of access to the memory unit 8 ends with the issuance of a read pulse, delayed by the element 29 for the read time, through the input 44 of the synchronizer 11 to the installation input of the trigger 72. The trigger 72 returns to its original state and blocks the passage of clock pulses to the output 47. In addition, the pulse from the input the delay element 29 passes through the OR element 26 to the installation inputs of the registers 1, 2, 3.

After the editing process of the corresponding section of the text document has been completed, the user identification code is again entered into register 1, the section code is entered into register 2, but now the editing completion signal is transmitted through input 36 to the single input of trigger 73, which opens up element 76 with high potential and the clock pulse with output 48 of the synchronizer 11 through the element 25 OR is fed to the input 57 of the selector 10. The operation of the selectors 9, 10 and register 4 is carried out similarly to the process described above. The difference is that in this case, the pulse from the output of the delay element 28 does not pass through the And element 13, as it was before, but through the And element 14 to the recording control input of block 8.

In accordance with the adopted example, at this point in time, the selector 9 with high potential will open the elements 18 And groups. As a result of this, the information input 37 of the device through the elements 18 AND, elements 21 OR will be connected to the information input of the block 8 of the memory.

By the signal from the output of element 14 AND, the contents of the edited section of the text document are recorded in the memory unit 8. After that, by the same recording pulse delayed by the delay element 30 for the recording time, firstly, through the input of the synchronizer 45, the trigger 73 is set to its initial state, blocking the further passage of pulses from the output of the And element 76, and secondly, through the OR element 26 are set in initial state registers 1, 2 and 3.

If the codes of register 2 and the upper bits of register 4 did not match, then a signal is generated at the output of the comparator, which is fed to the single input of trigger 22, setting it to a single state. With a high potential from a single output, trigger 22 opens one input of an And element 12, to the other input of which shift pulses of generator 74 of synchronizer 11 are received through output 46.

The shift pulses are fed to the input of the shift register 4 and to the counting input of the counter 6, which counts their number. The length of counter 6 is selected based on the dimension of the binary-decimal representation of the numbering of sections of text documents, so that after counting the number of all shifts, as a result of which one section number in the upper bits of the shift register is replaced by the next one in order, an impulse appears at the output of the transfer of counter 6. This pulse, firstly, through the element 24 OR returns the trigger 22 to its original state, blocking the further arrival of shear pulses through the element 12 AND to the inputs of the register 4 and counter 6, secondly, it enters the counting input of the counter 7 sections and, in thirdly, through the OR element 23, this pulse is delayed by the element 27 for the time the shift ends in the register 4 and arrives at the synchronizing input of the comparator 5.

If the codes being compared coincided, then a pulse appears at the output A of the comparator 5 and the process is repeated as described above when the codes match.

If the code of the section number of the register 2 and the next code in the higher bits of the register 4 did not match again, then a signal appears at the output of the comparator 5. The latter again sets the trigger 22 in a single state, thereby providing the input to the inputs of the shift register 4 and the counter 6 of the shift pulses from the generator 74, and the further process of comparing the codes is repeated again.

If the section of the text document requested by the user is not among the sections to which he is admitted, then after comparing the code of register 2 with all the codes entered in register 4, counter 7, counting the comparison cycles, will record the fact that the codes do not match by issuing a transfer pulse to its output. This pulse, firstly, is output to the device 40 as a signal of unauthorized access to the corresponding section of the text document, and secondly, through the OR element 24, it arrives at the installation input of trigger 22, returning it to its original state.

Thus, unlike known devices, this device provides reliable delimitation of user access to editable sections within the same text document.

Sources of information

1. US patent No. 5144556, cl. G 06 F 15/38, 15/40, public. 1992

2. US Patent No. 5129083, cl. G 06 F 12/00, 15/40, public. 1992 (prototype).

Claims (1)

A device for restricting user access to sections of text documents containing a first register, the information input of which is the first information input of the device, and the synchronizing input is the first synchronizing input of the device, the second register, the information input of which is the second information input of the device, and the synchronizing input is the second synchronizing the input of the device, the memory unit, the information inputs of which are connected to the outputs of the corresponding elements OR groups, addressed to the moves of the memory block are connected to the corresponding outputs of the third register, and the outputs of the memory block are connected to one of the inputs of the corresponding elements of the first group, the outputs of which are the information outputs of the device, the second group of elements of I, one of whose inputs are the information inputs of the device group, and the outputs are connected to the inputs corresponding elements OR groups, a synchronizer, the first and second control inputs of which are the first and second control inputs of the device, a trigger, a single output of which one connected to one input of the first AND element, the other input of which is connected to the shear output of the synchronizer, the first, second and third elements OR, the first, second, third and fourth delay elements, characterized in that it contains a selector of sections of text documents, the information input of which connected to the output of the first register, the clock input is connected to the first clock output of the synchronizer, and the control outputs are connected to the inputs of the corresponding elements of the first and second groups, the address selector is fishing, the information input of which is connected to the output of the second register, the information output is connected to the information input of the third register, the synchronizing output is connected to the synchronizing input of the third register, the shift register, the information input of which is connected to the information output of the section selector of text documents, the synchronizing input is connected to the synchronizing output section selector of text documents, and the shift control input is connected to the output of the first AND element, the first counter, counting input which is connected to the output of the first AND element, the transfer output of the first counter is connected to one input of the first OR element, the other input of which is connected to the synchronizing output of the text document section selector, and the output is connected to the input of the first delay element, the second counter, the counting input of which is connected to the output the transfer of the first counter, and the output is connected to one input of the second OR element, the other input of which is connected to the transfer output of the first counter, and the output is connected to the installation input of the trigger, compar a torus whose information inputs are connected to the outputs of the second register and the shift register, the synchronizing input is connected to the output of the first delay element, the first output of the comparator is connected to a single input of the trigger, and the second output is connected to the installation input of the second counter, to the third input of the second OR element, and to one input of the third OR element, the other input of which is connected to the second clock output of the synchronizer, and the output is connected to the synchronizing input of the partition address selector, the synchronizing output to The second one is connected to the input of the second delay element, the output of which is connected to the installation input of the shift register, the second element And, one input of which is connected to the first control output of the synchronizer, the other is connected to the output of the second delay element, and the output is connected to the input of the third delay element, with the input controlling the reading of the memory block and with the corresponding inputs of the AND elements of the first group, the third AND element, one input of which is connected to the second control output of the synchronizer, the other is connected to the output of the second a delay element, and the output is connected to the recording control input of the memory block and to the input of the fourth delay element, the fourth OR element, whose inputs are connected to the outputs of the third and fourth delay elements, and the output is connected to the installation inputs of the first, second and third registers, while the first the synchronization installation input is connected to the output of the third delay element, and the second synchronization installation input is connected to the output of the fourth delay element.

Images