SU1693610A2 - Device for microprocessor checking - Google Patents

Description

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(61) 1444783 (21) 4763201/24 (22) 11/27/89 (46) 11/23/91. Bul №43 (71) Rybinsk Aviation Technological Institute

(72) I.Z.Alterman, M.A. Gladshtein, V.M. Komarov and N.A. Shubin (53) 681.3 (088.8)

(56) USSR Author's Certificate Nfc 1444783, cl. G 06 F 11/28, 1987.

(54) DEVICE FOR THE CONTROL OF A MICROPROCESSOR

(57) The invention relates to computing and can be used in

building microprocessor devices to increase their reliability. The purpose of the invention is to expand the functionality by controlling the contents of the microprocessor stack pointer when executing stack instructions. The device for controlling the microprocessor contains a counter 1, a comparison circuit 2, registers 4 and 5, a block of permanent memory 6, an adder 7, a multiplexer 8, elements AND 3, 9-11, triggers 13, 14 and an element HE 12. The device is entered decoder 15, registers 16, 17, adder 18, comparison circuit. 19, counter 20, multiplexer 21, task block 22 stack boundaries, AND 23-25 elements, OR elements 27-29 and trigger 30. 30. Il, 1 tab.

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The invention relates to computing and is an improvement of the device according to the author. No. 1444783.

The purpose of the invention is to expand the functionality by controlling the contents of the microprocessor stack pointer when executing stack instructions.

The drawing shows a block diagram of the device.

The device for controlling the microprocessor system contains the first counter 1, the first comparison circuit 2 and the first 3 element I, the first 4 and second 5 registers, the persistent memory block 6, the first adder 7, the first multiplexer 8, the second 9, the third 10 and the fourth 11 elements AND, element 12, first 13 and second 14 flip-flops, decoder 15, third 16 and fourth 17 registers, second adder 18, second comparison circuit 19, second counter 20, second multiplexer 21, block 22 defining stack boundaries, fifth element And 23, the sixth 24 and the seventh 25 And elements, controlled microprocess p 26, the first 27, second 28 and third 29 element or the third flip-flop 30, the output 31 malfunction.

The device works as follows.

After power is turned on in the controlled microprocessor circuit 26, a reset signal RESET is generated, which is fed through the control bus to the reset inputs of the first counter 1, the second register 5 and the flip-flops 13, 14 and 30, which causes them to reset to zero. At the same time, the microprocessor command counter 26 is also set to the zero state. Then the microprocessor 26 begins the sequential selection and execution of commands for a given program. For the KP580 microprocessor, the latter can be single-byte, double-byte and three-byte. As a result, the address of the next command may be greater than the address of the previous command by one, two or three lower-order units, provided the microprocessor functions correctly. In addition, there are transition instructions in the microprocessor's instruction set, which can abruptly change the contents of the microprocessor instruction counter.

The moment of reading the first byte of the command is easily identified by the coincidence of signals on the sampling lines of the first byte of the command (M1) and reading memory (MEMR), microprocessor control bus 26. At this point, the third element AND 10 and the code of the first byte of the command set to this data bus time

is fixed in the first register 4. This byte goes to the address inputs of block 6 of the permanent memory, as a result of which a code will be set at its main output,

equal to the number of bytes in a command, and at the additional output - a command type code (the operational command is a transition command).

In particular, in order to control the microprocessor of the KP580 series, the codes stored in the block 6 of the permanent memory should correspond to the data given in Table 1. Each cell of this table corresponds to one of the 256 possible addresses. The code in each cell consists of two numbers. The right number corresponds to the decimal equivalent of the binary code generated at the main output of block 6 of the permanent memory and

0 is equal to the number of bytes (1,2 or 3) of the microprocessor command. The left digit corresponds to the state of the additional output of the block 6 of the permanent memory and is equal to one if the address byte corresponds to the transition command, otherwise it is zero.

Thus, the outputs of block 6 of the permanent memory immediately after the moment of fixation of the first byte of the order command in the first register 4 will set the code in accordance with the data in the table.

As a result, two situations are possible: the next command is not the command

5 transitions; the next command is the transition team.

In the first case, the input D of the first trigger 13 receives a logical O signal, and at the end of the signal from the output of the third element And 10 the first trigger 13 does not change its state. The byte code of the next command from the main output of the block 6 of the permanent memory is fed to the first input of the adder 7, and to the second input of it through

5, the first multiplexer 8 receives a code from the second register 5.

According to these data, the first adder 7 forms the sum and transfer (for the microprocessor KP580 multiplexer 8, the adder 7

0 and register 5 each contain two binary bits, since the binary byte code can only be 01.10 or 11). The sum goes to the input of the second register 5 and is written into it on the falling edge of the signal from the output

5 of the third element AND 10 due to the element NO 12. The signal from the output of the last passes also to the input of the increment of the first counter 1 through the second element I 9g if the transfer value at the output of the first adder 7 is equal to logical 1.

Thus, in the first counter 1 (most significant bits) and in the second register 5 (least significant bits) the expected address code of the first byte of the next command is generated. This code is fed to the input of the first comparison circuit 2. At the moment of extracting the first byte of the next command, microprocessor 26 generates its address on the address bus and the signals M1 and MEMR on the control bus.

If the microprocessor operates without failures, then the issued address coincides with the expected address coming from the first counter 1 and the second register 5. In this case, the zero potential is set at the inverting output of the first comparison circuit 2, which ensures a passive logic level at the output of the first And 3 element.

If there is a failure, then the addresses will be unequal, a logical unit signal appears at the output of the first comparison circuit 2. The coincidence of this signal with the active signal from the inverse output of the first trigger 13 and the signal from the output of the third element And 10 triggers the first element And 3, sets the second trigger 14 and the output of the third element OR 29, i.e. output 31 of the device, the active signal indicating a malfunction of the microprocessor.

If the next command is a transition command, then a single signal will be set at the additional output of block 6 of the permanent memory. As a result, on the falling edge of the signal from the output of the third element AND 10, thanks to the element NOT 12, the first trigger 13 goes into one state. The signal from its inverse output blocks the control of address matching when the next command is extracted using the first element And 3. In addition, the first multiplexer 8 switches and it connects the lower bits of the address of the controlled microprocessor to the second input of the first adder 7.

Thus, when extracting the first byte of a command, the control following the transition command is not performed, and its address plus the command byte (the expected address of the next command) is recorded in the first counter t and the second register 5. The high-order address bits in counter 1 are produced by the output signal the fourth element And 11, whose operation is permitted by a single signal from the output of the trigger 13,

The entry of the least significant bits, which are the sum of the lower bits of the address of the next command with its byte from the output of the first adder to the second register 5, as well as the transfer account from the output of the adder 7 to counter 1, occurs quite similarly to the first case. In addition, after reading the command following the transition command (if it is, of course, not the transition command itself), the first trigger returns.

0 13 to the logical O state and, therefore, the monitoring mode is restored. Control over program counter changes when executing transition commands

5 is conducted in the device based on the control of the contents of the microprocessor stack pointer. If the program counter fails, the transition command executes a false command stream;

As a result, the stack pointer is out of range, which can be determined in advance by the programmer.

In addition, the possible failure of the microprocessor's stack pointer itself becomes

5 the reason for the incorrect installation of the software counter that is not detectable by the described part of the device.

To control the behavior of the microprocessor stack pointer 2, the decoder 15

0 is configured to select only one command. - Loading the stack pointer. In the KP580 microprocessor command system, this command is the command LXf SP, D16. When in the first register 4 is fixed

5 the code of this command, a single signal from the output of the decoder enables the operation of the fifth element AND 23. As a result, in the following cycles of the execution of this command, the MEMR signal on the control bus is performed

0 entry in registers 16 and 17 of data addressing the top of the stack.

The same data is recorded in the index of the stack of the microprocessor 26. Simultaneously with the recording of data in registers 16 and 17 on the signal from the output of the element And 23, the second counter 20 is cleared. The data on the top of the stack from the outputs of registers 16 and 17 are constantly present on the first the input of the second adder 18. On the second

0 the input of the adder 18 receives the code from the output of the counter 20, which is the current offset of the pointer of the microprocessor 26 or, otherwise, an index relative to the top of the stack.

5 The width of the counter 20 is generally determined by the width of the address arriving at the first input of the adder 18. However, the width of the counter 20 can be significantly reduced taking into account the implementation of real programs. In these cases, the higher bits of the second input of the adder

18 must be connected to the potential of Log.1, since the adder 18 implements the function of subtracting the top of the stack and the index, i.e. In order to correctly track the microprocessor stack pointer, the index must be set at the second input of the adder 18 in the additional code.

At the moment of accessing the stack of microprocessor 26, a STACK signal is generated on the control bus that unlocks AND 24 and 25. When the cycle is implemented, the MEMW microprocessor signal from the control bus through the AND 25 element enters the decrement input of the second counter 20, resulting in the state is decremented by one, and the code at the output of the adder 18 is also decremented by one. Thus, at the output of the adder 18, the expected index code of the microprocessor stack 26 is formed. This code is fed to the input of the second comparison circuit 19.

If microprocessor 26 operates without failures, then the issued cell address of the stack matches the expected address from adder 18. In this case, the inverting output of the second comparison circuit 19 sets zero potential, which ensures a passive logic level at the input of the second element OR 28.

If the stack pointer fails, then the addresses are not equal, at the output of the second comparison circuit 19 a logical signal 1 appears which is through the element OR28 passes to the input of the third trigger 30. It will be set to one at the time of the cut-off of the MEMW signal the first element OR 27 is supplied to the synchronous input of the third trigger 30. A single signal from the trigger 30 is supplied through the third element OR 29 to the output of the device 31 and indicates the microprocessor 26 does not work correctly.

Thus, after the implementation of the cycle of writing information to the stack at the output of the second adder 18, the address of the last filled stack cell is always set. The same address is recorded in the stack pointer of the microprocessor 26 upon completion of the execution of the stack instruction.

If the microprocessor stack pointer 26 fails, then in the Read cycle from the stack, the microprocessor 26 outputs the address of the stack cell to the address bus corresponding to the address at the output of the adder 18. Then the inverting output of the second comparison circuit 19 establishes zero potential, indicating that the addresses are equal her entrances. The result of the address comparison is fixed in the third trigger 30 on the front of the synchronizing signal, which arrives at the corresponding input of the trigger 30 through the AND 24 and OR 27 elements at the time of the STACK and MEMR signals on the microprocessor control bus 26.

At the same time, the same signal

0 to the input of incrementing the counter 20, increases by one the index at its output, respectively, increasing by one the index at its output, respectively increasing by one the output address of the sum of 5 torus 18. This is fully consistent with the actions of the microprocessor 26, which at the end of each cycle Read from the stack increases the contents of the stack pointer by one.

0 In the case of the microprocessor 26 stack pointer fixation, an error signal is fixed at the device output 31 when executing a cycle. The reading from the stack is performed similarly.

5 To control the stack depth violated due to false transitions of the program counter of the microprocessor 26, the second multiplexer 21 maps the index at the output of the counter 20 to a code,

0 installed in block 22 tasks. The binary output code of task block 22 connects to the inverting output of multiplexer 21 a corresponding bit from the counter 20 output. This bit is selected by the user using task block 22 as a stack boundary, starting from the program executed by the microprocessor. For example, if the stack depth is 64 memory locations, then 6

0-7 is the counter's 20 bit. The appearance of a logical O signal at it at the time of the stack program implementation will indicate a stack overflow, i.e. about the violation of the selected depth.

5 As a result, a single signal appears at the inverse output of multiplexer 21, which through the element OR 28 enters the D input of the trigger 30 and causes its installation. Single output signal

0 trigger 30 through the element OR 29 is fed to the output of the error 31 of the device, thereby indicating a violation of the correct functioning of the microprocessor 26.

5 If the microprocessor 26 operates without failures, then when implementing the access to the stack at the selected input of the multiplexer 21 there is always a logical signal 1. which cannot transfer the trigger 30 to the active state.

Thus, the device constantly monitors the correctness of the change in the program counter (with the exception of the transition points) and the microprocessor stack pointer. The device also controls the depth of the stack, which indirectly characterizes the correctness of microprocessor transitions according to the program.

The error signal from the output of the device can be used in various ways, for example, to light or sound the microprocessor to malfunction, to interrupt or reset the microprocessor to restore the calculations after a failure, and to connect a backup microprocessor.

Claims (1)

Invention Formula A device for controlling a microprocessor auth.St. No. 1444783, characterized in that, in order to extend the functionality by monitoring the contents of the microprocessor stack pointer when executing stack instructions, it contains a decoder, a third and fourth registers, a second adder, a second comparison circuit, a second counter, a second multiplexer, a boundary setting block the stack, the fifth, sixth and seventh elements AND, the first, second and third elements OR and the third trigger, and the information input of the third register is connected to the input of the device for connection to the data bus is controlled microprocessor, the output of the third register is connected to the information input of the fourth register, the output of which and the output of the third register form the first information input of the second adder, the second information input of which and the information input of the second multiplexer are connected to the output of the second counter, whose reset input and synchronization inputs of the third and fourth registers are connected to the output of the first item, And, the first the input of which is connected to the output of the decoder, the information input of which is connected to the output of the first register, the first information input of the second comparison circuit is connected to the input of the device for connection to the address bus of the controlled microprocessor, the output of the second adder is connected to the second information input of the second comparison circuit, the first inputs of the sixth and the seventh elements And connected to the input of the device for connecting to the output of the signal access to the stack controlled by the microprocessor, the second inputs of the fifth and sixth element The units And are connected to the input of the device for connecting the readout memory of the controlled microprocessor, the second input of the seventh element And is connected to the input of the device for connecting to the write output to the memory of the controlled microprocessor, the inverse input of the fifth element And is connected to the input of the device for connecting to the output the sign of the first byte of the command of the controlled microprocessor, the direct and inverse outputs of the first OR element, and the inputs of the increment and decrement of the second counter are connected respectively to the outputs of the sixth and seventh elements And, the output of the stack boundary setting block is connected to the address input of the second multiplexer, the inverse output of which is connected to the first input of the second OR element, the second input of which is connected to the inverse output of the second comparison circuit, the outputs of the first and second elements OR connected respectively to the C- and D-inputs of the third trigger, the R-input of which is connected to the input of the device for connection to the reset output of the controlled microprocessor, the outputs of the second and third triggers are connected respectively But with the first and second inputs of the third OR element, the output of which is the output of a device failure. Table continuation Table continuation