SU1564620A2 - Device for control of microprocessor system - Google Patents

Abstract

The invention relates to computing, can be used in the construction of microprocessor-based computing systems with memory, divided into blocks, and is an improvement of the invention according to the author. N1283760. The purpose of the invention is to expand the functionality of the device by allowing arbitrary access to any of the N memory blocks by setting the address of the memory block from the microprocessor. This is achieved by the fact that the device additionally contains the element NOT 11, the third element And 12, the third decoder 13. 1 Il.

Description

The invention relates to computing, can be used in the construction of microprocessor-based computing systems with memory, divided into blocks and is an improvement in autosv. No. 1283760.

The purpose of the invention is the expansion of the functionality of the device by enabling arbitrary access to any of the N memory blocks by setting the memory block from the microprocessor.

The drawing shows a functional diagram of the device.

The device contains blocks 1.1 1. N memory, multi-mode buffer register 2, counter 3, first 4 and second 5 decoders, indication trigger 6, elements AND 7.1 - 7.N of the first group, elements AND 8.1 - 8.N of the second group, first 9 and the second 10 AND elements, the element NOT 11, the third AND element 12 and the third decoder 13,

The device has the first 14 and second 15 data inputs / outputs, address input 16 and output 17, input 18 of the Machine clock synchronization, input 19 of information recording permission, input 20 of synchronization, input 2 '= input permission, input 22. start, output 23 signaling the end of work and the output 24 signaling the beginning of work.

The device operates as follows.

By a signal from input 22 of the start of the device, the indication trigger 6 is set to one, the state signal from the output 24 of the alarm 'The start of operation of the device signals the start of operation of the device.

The multiprocessor can start accessing any of the 1.1 - 1 .N memory blocks. For this, counter 3 records the address of the desired memory block. Counter 3 is an external device for the microprocessor; it is accessed by an OVT command. Writing data containing the address of the desired memory block to counter 3 is as follows.

The microprocessor at the address input 16 supplies the address of the counter 3, which is input to the third decoder 13. If this address really matches the address of the counter 3, the third decoder 13 generates a single enable signal at the input of the third element And 12.

In parallel with the counter address 3, the microprocessor sets a status byte, which through the first input 14 of the device goes to the input of the multi-mode buffer register 2. Upon the arrival of synchronizing pulses from the microprocessor, the status byte is input to the multi-mode buffer register 2. From the output of the multi-mode buffer register 2, two signals that allow recording to an external device also go to the input of the third element 'AND 12.

Therefore, the signal from the information recording permission input 19 passes through the third element And 12 to the corresponding input of the counter 3 and records one of the blocks 1.1 - 1.N of memory previously set by the microprocessor to the first input-output 14 of the device and received. counter input 3.

From the output of counter 3, the address of one of the blocks 1.1 - 1 .N of the memory is fed to the input of the second decoder 5. At one of the outputs of the second decoder 5, an enable signal appears to access the desired memory block 1.1. Now the microprocessor can access the memory unit 1.i defined by the value of counter 3, which is its address.

Reading information from the cell block 1 „i memory is as follows.

The microprocessor at the address input 16 supplies the cell address of the block l.i memory.

In parallel with the cell address, the microprocessor sets the status byte, which through the first input-output 14 of the device is supplied to the input of the multi-mode buffer register 2. The status byte is written to the multi-mode buffer register 2 as described. The enable signal from the output of the multi-mode buffer register 2 is fed to the inputs of the elements And 8.1 - 8.N. Of the second group.

Since only one of the conclusions of the second decoder 5 mouth

1.i memory byte consist-20 input-configured first decoder 4. In this case, from the output of the first decoder I · Jura 4, the enable signal is fed to the input of the second element And 10. Upon arrival of the signals to the input 18 of the machine clock cycles of the device and the input 20 of the device synchronization at the output of the second element And 10 a signal is generated that increases the value of counter 3 by one. Changed to one, the address of the memory block located in counter 3 is fed to the input of the second decoder 5 and causes switching on its output. As a result of this, the memory unit 1.i is connected to the control buses of the microprocessor.

The device if the value of the block address ends the operation, counter 3 matches. 1.N + 1. In this case, the enable signal for working with the memory unit 1.i, which is input to the element And 8.ί of the second group, is updated, the signal from the input information permission 21 is passed through the element And 8.ί of the second group and goes to the input of block 1.1 memory. The data read from the memory cell of the memory unit 1.1, determined by the address at the address input 16, enters the microprocessor through the first input-output 14 of the device.

Recording information in the cell block 1.1 memory is as follows.

The microprocessor at the address input 16 provides the address of the unit cell tee. In parallel with the address, the microprocessor sets, which, through the first turn 14 of the device, enters the input of the multi-mode buffer register 2. The status byte is written to the multi-mode buffer register 2 as described. The enable signal from the output of the multi-mode buffer register 2 is fed to the inputs of the elements And 7.1 - 7.Ν of the first group. But since one of the outputs of the second decoder 5 has a permission signal for working with the memory unit 1, ί, which is fed to the input of the element And 7 первой i of the first group, the signal from the input 19 of the information recording permission passes only through the element And 7.i of the first group and goes to the input of the li memory block. According to this signal, the data received from the microprocessor through the first input-output block 1.i input to the block cell with the address

Thus, the microprocessor can access any of the cells of the block 1.1 memory.

.If it is necessary to refer to some other memory block 1.i, the microprocessor can switch the memory blocks. If j ψ i + 1, then the switching of memory blocks occurs according to the write command (OVT) of the address of the new memory block in counter 3, as described.

If j = i + 1, switching is performed automatically when the device is in memory, memory 1.1 is recorded, defined address 16.

the signal from the last output of the second decoder 5 is fed to the input of the indication trigger 6 and sets it to the zero state. At the output 23 of the alarm at the end of the device, a signal appears about the end of the device.

In addition, the signal from the last output of the second decoder 5 is fed to the input of the first element And 9. With the arrival of the signal at the input 18 of the synchronization of machine cycles of the device, the counter 3 is reset to zero.

The device is finished.

Claims (1)

Claim A device for controlling a microprocessor system according to ed. St. No. 1283760, characterized in that, in order to expand the functionality of the device by providing the possibility of arbitrary access to any of the N memory blocks by setting the address of the memory block from the microprocessor, the device contains the element NOT, the third element And and the third decoder, moreover, the input of the element is NOT connected to the second inverse output of the multi-mode buffer register and the fourth inputs of the elements of the first And. group, the output of the element is NOT connected to the first input of the third element And, the second input of which is connected to Ode to enable recording of device information, the third input of the third element is connected to a cell or group of cells with a specific address that is connected to the first inverse output of the multimode buffer register, the fourth input of the third element is connected to the output of the third decoder, the output of the third element And is connected to the input permissions of the counter, the information input of which is connected to the first input / output of the device data, the input of the third decoder is connected to the address input of the device.