SU1674137A1 - Data and programs storage control unit - Google Patents

Abstract

The invention relates to the field of computing and can be used to manage memory in microprocessor systems. The purpose of the invention is to increase the speed of the device. The device contains a converter of 1 codes, elements AND 2, 3, element NOT 4, counter 5, element OR 6, trigger 7, elements AND-HE 8, 9, address selectors 10, 11, information 12 inputs, input 13 sampling commands, input 14 reads of the device, input 15 of the state strobe, input 16 of the load, address inputs 17, selection input 18, sample outputs of the first 19 and second 20 pages of memory. 1 il.

Description

Fig /

The invention relates to the field of computing and can be used to manage RAM in microprocessor systems.

The purpose of the invention is to increase the speed of the device.

Figure 1 is a diagram of the device for managing the memory of programs and data; figure 2 - timing diagram of the device.

In Fig. 1, a code converter 1 is designated (may be made as a permanent storage device), elements AND 2, 3, element 4, counter 5, element OR 6, trigger 7, elements AND-HE 8, 9, address selectors. 10, 11, information inputs 12, command sampling input 13, device reading input 14, state strobe input 15, boot input 16, device address inputs 17, device selection input 18, first 19 and second memory page sampling outputs 20, output 21 elements OR, direct output 22 trigger.

Information inputs 12 of the device are connected to the data bus of the microprocessor system (not shown in figure 1). Device Inputs Sample command 13, Read 14, Status gate 15 are connected to the outputs of the microprocessor control system bus M1, DBIN, STB, respectively. Input 16 Device loading is connected to one of the bits of the output port of the microprocessor system. The address inputs of the device 17 are connected to the address bus of the microprocessor system. Input 18 of the device selection is connected to the output of the memory access control bus of the microprocessor system. The device outputs Sampling the first page of memory 19 and Sampling the second page of memory 20 are connected to the inputs of a sample of crystals of the instruction memory and data storage circuits, respectively (the memory circuits are not shown in Fig. 1).

In the initial state, the inputs 13-18 of the device and the outputs 19, 20 of the device are set to O. The input 16 of the device is set to 1. The contents of the counter 5 and the D flip-flop 7 are zero. In the code converter 1, by the addresses corresponding to the microprocessor's command codes, the command length is written in bytes, for example, code 3 is written for the LHLD command at address 2АAN. Consider the operation of the device when the microprocessor-based LHLD system command is executed. The timing diagram of the device is presented in figure 2.

In the first machine cycle at the second input of the element And 3 is set 0y, prohibiting the passage of a pulse from the input) 5

A state gate of the device to the subtracting input of the counter 5. At input 13, the selection of the device command is set to G, allowing the operation of code converter 1 and setting D-flip-flop to 1 to the first input of the AND-NOT element 1, preparing its operation. To the selection input of the device 18, 1 is applied. At the output of the element IS-HE 8, O is set, which decides the operation of the address selector 10, i.e. sample command code from the command memory. The command code LHLD 2AH arrives at the information inputs 12 of the device, the output of the code converter 1 is set to code 3. The rear edge of the pulse at the input 14 Read the device, pass through the prepared And 2 element, initiates writing of the code 3 to the counter 5, At the output of the OR 6 element set 1, which enters the second input element And 3, preparing his work. At input 13, the device command fetch sets Oh, prohibits the operation of code converter 1 and writes to counter 5. At the input of the selection

5, device 18 is set to O by prohibiting operation of the memory circuits.

In the second and third machine cycles, the pulse from the input 15 of the gate of the state of the device through the prepared element And 3

0 enters the subtracting input of counter 5. The contents of counter 5 are 2, and in the third machine cycle, 1. The state of D-flip-flop 7 remains unchanged. The second and third bytes of the command code are sequentially selected from the command memory.

In the fourth machine cycle, the pulse from the input 15 The state gate of the device through the prepared element I 3 enters the subtracting input of counter 5. The contents of counter 5 become equal to zero. At the output of the element OR 6, a falling edge of the logical signal is formed, which is inverted on the element 4 and transfers the D-flip-flop to the state O. At the first

The 5 input of the element AND-NOT 9 is set to 1, preparing its operation. At the second input of the element, And 3 is set to O, prohibiting subsequent subtractions from the counter 5. To the input of the device selection, 18 is fed 1. At the output of the NESHE element 9, O is set to allow the operation of the address selector 11, i.e. sample data from the data memory. At the end of the machine cycle at the input of the device selection 18

5 is set to 0, prohibiting the operation of the memory circuits.

In the fifth machine cycle, the second data byte is selected from the data memory.

It is assumed that, for the device, the instruction memory is executed in the form of a ROM or one memory storage device with hardware boot circuits.

Consider the operation of the device in the mode of loading the memory of commands, when the input to the 16th device loading is O. This can be done with a couple of commands of the MVIA microprocessor. Out

D-flip-flop 7 enters state 1 regardless of the signals at its other inputs. The operation of the converter 1 codes, as well as the recording and subtraction of the counter 5 is prohibited. At the first input of the element AND-NOT 8 is fed G. When filing 1 at the input of the selection of the device 18, the operation of the address selector 10 - the instruction memory selector is permitted. Therefore, program writing and reading of the instruction memory is allowed.

Claims (1)

Claims An apparatus for managing memory of programs and data, comprising a trigger, an element is NOT. the first and second elements are AND- NOT, the first and second address selectors, the same inputs of the address selectors are combined and are the device's address inputs, the outputs of the first address selector are the sample outputs of the first memory page of the device, the outputs of the second address selector the second page of the device memory, the outputs of the first and second elements AND-NOT are connected respectively with the inputs of the prohibition of sampling the first and second address selectors, the first input of the first of the NAND element is connected to the direct output of the trigger, the second inputs of the NAND elements are not combined and are the device selection input, characterized in that, in order to improve the device speed, a code converter, a counter, the first and second elements are entered into it. the OR element, the inverse output of the trigger is connected to the first input of the second NAND element, the information inputs of the code converter are the same inputs of the device, the outputs of the code converter are connected to the information inputs of the counter, the first input of the first elec The I input is connected to the first sample input of the code converter and to the input of the installation in Trigger G and is the input of the command selection of the device, the second input of the first element I is the input of the device, the output of the first element I is connected to the input of the counter mode setting And is the input of the state gate of the device, the output of the second element AND is connected to the subtractive input of the counter, the information outputs of the counter are connected to the inputs of the OR element, the output of which is connected to the second input of the second element Both and with the input of the element NOT, the output of the element is NOT connected to the trigger synchronization input, the installation input into the trigger O is connected to the second sampling input of the code converter, to the third input of the first AND element and is the input of the device load. Fig.i