SU879563A1 - Device for checking programs - Google Patents

Description

The invention relates to the field of computer technology, in particular to the organization of monitoring and debugging programs. A device is known for controlling the passage of programs l, in which a zone memory consists of three main parts: a high-speed storage unit for storing addresses, selection and storage schemes for addresses, readout schemes and visual indication of fixed addresses. The disadvantage of the device is low reliability of the control programs. The closest technical solution to the invention is device 2. The processing system contains the main memory, a block of commands, a memory cone unit, a channel block, an execution unit, a control panel and a device consisting of a switch, an upper address limit register, an address lower register register, a lower program address register, an address number register used in the system, from the lower address of the program to the upper address of the program, blocks for comparing the boundaries of addresses, logic and pulse distributor. The disadvantage of the prototype lies in the low reliability of the control of programs, since the device does not allow to fix the path of the program. The device checks whether the addresses of the commands being executed are included in the allowed address range, but the addresses of the commands used in the programs with regard to transitions and cyclic sections are not fixed. The aim of the invention is to increase the reliability of program control. This goal is achieved by the fact that two OR elements, a counter (addresses), two memory blocks, an AND block and a trigger connected to the outputs are entered into a device for controlling programs containing two registers, a switch, a comparison block and a control block. the first inputs of the switch connected by the first output through the first address register connected in series and the first element OR to the first input of the control unit, and the second input through the second address register and the address counter to the first inputs of the first and second respectively locks the memory, the second inputs of which are connected to the lane vym input control unit, a second input connected to the second row WMOs first register output connected through the comparator to the second input of the control unit. The third input of the latter is connected to the second output of the comparison unit, and the third output to the second input of the comparison unit connected by the third input to the output of the counter connected to the second and third inputs respectively to the second output of the comparison unit and to the output of the first OR element whose input is connected to the first the input of the block of elements And, connected by the second input to the fourth output of the control unit, and the output to the fourth input of the counter and to the second input of the second address register connected by the output through the second element OR with trigger input. The switch information input is the device input. The drawing is given a functional diagram of the device. The device contains the switch 1 address counter 2, the first 3 and the second 4 address registers, the comparison unit 5, the trigger 6, the first 7 and second 8 elements OR, the block of elements AND 9, the control unit 10, the first 11 and second 12 memory blocks and memory cells ty 13, 13p and 14, - 14p. The device works as follows. In the initial state (the installation circuit of the device nodes in the initial one is not shown in the drawing) all the registers, the counter, the cells of the memory blocks do not contain information, the trigger 6 is in the state O, and the control unit is in the state of the signal from the trigger output 6. The block connects the input 15 of the device to the input of register 4 and counter 2. Alres of the initial command of the program (lower limit of the set of addresses of the commands) by the change signal of the command address is recorded in counter 2 and register 4. After the address of the national command write to register of the element 8 moves the trigger 6 into state 1. As a result, the switch disconnects the stroke 15 from the inputs of register 4 and count 2 and connects it to the input of register 3. This state of trigger 6 remains until the device is reset condition. After that, the device is in standby mode, changing the address of the command on the command counter of the digital computer. The address of the next command, which the DVR proceeded to execute, by the command change signal, through block 1 is recorded in register 3. As a result, the signal from the output of the element OR 7 increments the contents of counter 2 and enters the input of the control unit 10, which in response to it sends a control signal to the input of the comparison block 5. The comparison block 5 compares the contents of register 3 and counter 2, i.e. compares the addresses of a new command with the address of the previous command increased by one. Depending on the result of this comparison, two modes of operation of the device are realized. If the contents of register 3 are equal to the contents of counter 2 (the addresses of the previous and subsequent commands differ by one, i.e., in the digital computer, commands with consecutive addresses are executed), the control unit 10, using the signal from the corresponding output of the comparison unit 5, blanks the register 3, and the device enters the mode of waiting for a change in the command executed in the digital computer (block 10 expects a signal from element 7). When a new team receives the address of register 3, 1 is added to counter 2 and the contents of register 3 and counter 2 are compared. If they are equal, register 3 is cleared again and the transition to the pending command change in the digital computer is performed. The operation of the device in this case corresponds to the execution in the digital computer of a continuous chain of commands with consecutive addresses. In this case, the contents of register 4 define the first

the command (the lower address of the set of addresses of commands) of the set of executed commands, and on counter 2, the expansion occurs, the upper limit of the set of addresses of the command

In the case when the contents of counter 2 and register 3 are not equal (that is, the address of the subsequent command differs from the previous one by a number other than one), the operation of the device corresponds to switching from one command set (with sequential addresses) to another. In this case, the signal from the corresponding output of the comparison block 5 of the counter 2 decreases by one (it returns to the address of the command from which control is transferred in the program). In addition, by this signal, from the outgoing unit of the control unit 10, to the inputs of the memory units 11 and 12, a control signal is supplied, according to which the contents of the register 4 and the counter 2 are written into checks 13 and 14i, respectively, then the contents of the blocks 11 and 12 are shifted by The first cell is in the direction of 13p and 14p cells, respectively. Thereafter, from block 10 to the input of block 9, a control signal is supplied, according to which the contents of register 3 is transferred to register 4 and to counter 2, and register 3 is then reset.

Thus, as a result, the device enters the mode of waiting for the address of the new command from the digital computer. In register 4 and counter 2, the lower address of the new set of command addresses is recorded, and in cells 13j and 14 (after shifting the contents of blocks 11, 12), respectively, the lower and upper boundary addresses of the previous instruction set with consecutive addresses.

Thus, if the input of the device is supplied from the counter of commands of the digital computer, the addresses of commands executed in the digital computers, after the end of the controlled program in the 13, -13p, 14, -14g cells, blocks 11,12, the boundary addresses of sets of executed commands with sequential addresses will be fixed i.e. the path of the program will be recorded. In the case when the command set consists of one command, the contents of the 13, - 3p and 14, - 4p cells will be equal to each other and the address of this particular command.

The device allows to increase the reliability of program control, as it provides for fixation of the program path. The boundaries of command sets with consecutive addresses in the device memory are fixed in the order in which they were executed. In the case of cyclic programs, all past cycles are also recorded in the memory. The contents of the device memory in a known manner can be printed.

Claims (2)

Invention Formula A program control device comprising two address registers, a switch, a comparison unit and a control unit, characterized in that, in order to increase the reliability of the program control, two OR elements, an address counter, two memory blocks, a block of AND elements and a trigger are entered into it connected by the outputs to the control inputs of the switch connected by the first output through the first address register connected in series, the first OR element to the first input of the control unit, and the second output through the second address register and the address counter the first inputs of the first and second memory blocks, respectively, the second inputs of which are connected to the first output of the control unit connected by the second output to the control input of the first address register connected by the output through the comparison unit to the second input of the control unit whose third input is connected to vttory ry output of the comparison unit, and the third output to the second input of the comparison unit connected by the third input to the output of the counter connected to the second and third inputs respectively to the second output of the comparison unit and to the output for the first OR element, whose input is connected to the first input of the AND element block connected by the second input to the fourth output of the control unit, and the output to the fourth input of the counter and the second input of the second address register connected by the output through the second OR element to the trigger input, and information switch input is device input. Sources of information taken into account in the examination of 879563. 8 1. US patent number 3935563, cl, 340-172.5, published. 1976. 2. US patent number 3931611, cl. 340-172.5, published. 1976 (prototype).  I ff one / t  f f fff