SU1151962A1 - Microprogram control device - Google Patents

Abstract

1. MICROPROGRAMMING CONTROL DEVICE containing two memory blocks, micro-instructions, a switch, a micro-command register and a condition checker, the output of the microoperations code of the micro-register is an output of the device, the output group of the micro-command register of the micro-instructions register is connected to the first input group of the condition checker, the second group of inputs of which is a group of inputs of the logical conditions of the device, the information input of the register of microinstructions is connected to the output of the switch, the first and second information the inputs of which are connected respectively to the outputs of the operation codes and logical conditions of the first and second microcommand memory blocks, the first and second outputs of the condition check block are connected respectively to the first and second control inputs of the switch, characterized in that, in order to reduce the equipment, it contains the first and the second address generation units, wherein the first and second control inputs of the first and second address generation units are connected respectively to the first and second outputs of the condition testing unit, the outputs of the first and second address generation units are connected respectively to the address inputs of the first and second microcommand memory blocks, the outputs of the address code of which are connected respectively to information inputs (L dami of the first and second address generation units). 2. The device according to claim 1, wherein each of the address generation units comprises a register, a switch and an adder, the register output being connected to the information input of the adder and being the output of the block, the information input of the register connected to the output from the switch, the first and the second control inputs of which are respectively the first and second control inputs of the block, the first information input of the switch is connected to the output of the adder, the transfer input of which is connected to the potential potential bus, the second second information input of switch is informa-, insulating the input unit.

Description

The invention relates to computing and can be used in the construction of control automata. A firmware control device is known that contains a memory block, a micro-command register consisting of micro-operations floor, logical conditions and an address field, micro-instructions address counts and a condition-checking unit including a decoder, a group of elements AND and an IL 1 element. The disadvantage of this device is a low speed, since the duration of the automatic current is the sum of the counting time in the micro-command address counter, the micro-command sampling time from the memory block and its execution time in the automatic machine. It is also known a firmware control device containing a memory block, a micro-command register consisting of a field of micro-commands, a field of logical conditions and two address fields, a switch, a group of elements AND, an element OR, and an element NOT L2J. Although in comparison with the previous device, this device has a slightly higher speed (in it the duration of the automatic cycle is reduced by the counting time in the microcommand address counter), but it also has a low speed, since it cannot be used to sample the next microcommand. execution time in the operating machine of the previous microcommand. The closest in technical essence to the Invention is a firmware control device comprising two memory blocks, a switch, a register and a condition check block, with the first and second information inputs of the switch connected to the outputs of the first and second memory blocks, respectively; the output of the switch is connected to the information input of the register, the first output of which is the information output of the device, the second output is connected to the information input of the verification unit, conditions, the third output is addressable in Odom memory blocks ti second information input of the verification environment unit is a group of conditions of entry device, first and second output condition checking block soedi2J Nena respectively with the first and vtoipbiM enabling input switch 3J. The known device provides a significantly higher speed in relation to the previous ones, since in it the duration of the automatic clock is significantly reduced due to parallelization of the execution of the current microcommand and the selection of the next one. However, its drawback is the large amount of equipment used, since the total capacity of the two memory blocks significantly exceeds the minimum required memory capacity required for microprogram placement (the minimum required memory capacity when using firmware control devices is equal to the number of operator vertices in the graphs : their firmware). The purpose of the invention is to reduce the amount of equipment used. The goal is achieved by the fact that a microprogrammed control device containing two microinstructions memory blocks, a switch, a microinstructions register and a conditional verification unit, the microoperations code register of the microcommands is output of the device, the group of microprograms of logic codes of the register of microcommands is connected to the first group of inputs the condition test unit, the second group of inputs of which is the group of inputs of the logical conditions of the device, the information input of the micro-register register is connected to the switch output the first and second informational inputs of which are connected respectively to the outputs of the operation codes and logical conditions of the first and second microcommand memory blocks, the first and second outputs of the condition checker are connected respectively to the first and second control inputs of the switch, the first and second address generation blocks are inserted , wherein the first and second control inputs of the first and second address generation units are connected respectively to the first and second outputs of the condition testing unit, the output of the first and second blocks The shackles of the formation of the address are connected respectively to the address inputs of the first and second memory blocks of microinstructions, the outputs of the address code of which are connected respectively to the information inputs of the first and second blocks of the formation of the address. In addition, each of the address formation blocks contains a register, a switch, and an adder, with the B.OUT register connected to the information input of the adder and the output of the block, the information input of the register connected to the output of the switch, the first and second control inputs of which are first and second control inputs of the block, the first information input of the switch is connected to the output of the adder, the transfer input of which is connected to the single potential bus, the second information input of the switch is information input block. FIG. 1 shows a flowchart of the proposed firmware control device; FIG. 2 is a functional diagram of a condition checking unit; FIG. in fig. 3 is a functional diagram of an address generation unit; in fig. 4 and 5, respectively, the diagram of the microprogram and the principle of its placement in the memory blocks of the proposed device; in fig. 6 principle of placement in the memory blocks of the proposed firmware device described in the description of the known device L3 J; Fig. 7 shows the placement of this firmware in the memory blocks of the known device; 8 is a graph of volume reduction when using the proposed device in comparison with the known device depending on the percentage of the number of conditional vertices to the operator ones in the graph-schemes of the microprograms used in them. The microprogram control device (Fig. 1) contains the first 1 and second 2 blocks of the address generation, the first 3 and second 4 blocks of the microinstructions memory, the switch 5, the register of the microinstructions 6, the conditioner 7, the outputs 8 and 9 of the first and second formation blocks addresses, outputs 10 and 11 of the operation code and logical conditions of the first and second microinstructions memory units, outputs 12 and 1: 3 of the address code of the first and second microcommands memories, respectively, output 14 of the device, group 15 outputs of the logic register register of microinstructions , a group of 16 inputs of logical conditions, the first 17 and second 18 outputs of the condition checker. The condition checker (Fig. 2) contains a decoder 19, a group of elements And / (K is the number of logical conditions), an OR element 21 and a NOT element 22. The address generation unit (Fig 3) contains an adder 23, a switch 24, a register 25 and adder transfer input 26 connected to a single potential bus. The operation of the device will be considered on the example of the execution of the microprogram, the graph-diagram of which is shown in FIG. 4. Here y {(where i 1,10 is the control part of the i-th 1 shkrokomandy, d: (where j 1, 3) is the code j-ro of the checked logical condition, V g, (where n 0 , 5) and C "(where m is 0.3) the addresses of the cells of blocks 3 and 4 of memory, respectively, along which the microcommands are stored, while here it is assumed that the difference between the values of addresses B and C and C is one. The placement of micponporpaMhfti in blocks 3 and 4 of the memory of the proposed device is shown in Fig. 5. In the device, the address of the next micro command, read from the memory block (first 3 or second 4), is equal to either the previous address The commands of this block, incremented by one, or determined by the address field of the previous microcommand of the adjacent memory block. The device works next. In the initial state, register 6 is zeroed out, and the initial address B, j is entered into the register of the first address generation unit 1 firmware (synchronization circuit, zeroing and entering the address B in the drawings for the purpose of simplification are not shown). Since the first information input of the condition verification unit 7 receives a zero code, the signals of a logical unit and a logical zero, respectively, are set at the first 17 and second 18 outputs of this block. The signal of the logical unit allows recording via the switch 5 controlling parts of the microcommand. read from the first memory block 3 at address Bj, into register 6, and also writing address B. to the register of the first address formation block t from the adder output and the address from output 12 of the first memory block 3 to the register of the second address formation block 2 (for currently readable microcommand, this address is null m). Over, information is written into the registers of the blocks f and 2 of the formation of the address and into the register 6 by a single pulse. The micro command read from the first memory block 3 at address b becomes the current one and is executed. Simultaneously with its execution, the next microcommand from the first memory block 3 at address B is read, as well as the microcommands from the second memory block 4 at the zero address. However, because in the code field of the checked logic level of the current microcommand there is a zero code, the logical signals do not change on the first -17 and second t8 outputs of the condition checking unit 7. This leads to the fact that register 6 will contain the value of y, a micro-command read from the first memory block 3 at address 6 ,. Since the zero code is also found in the code field of the checked logical condition of this microcommand, the next one written in. The micro-command register 6 will be a micro-command read from the first memory block 3 at address B, while the address of the output of its adder will be written to the register of the first address generation block 1, and the address Ce from the first 12 output will be written to the register of the second address generation block 2 block 3 Memory. During the execution of this microcommand, two possible next microcommands from the first memory block 3 at address B, and the second memory block 4 at address Cj will be simultaneously read. Since the condition code S is in the code field of the checked logical condition of the current microcommand, depending on its execution or non-fulfillment, the logical signals on codes 17 and 18 of the conditioner 7 are changed or not. So, if condition X is fulfilled, then on the first 17 and second: i8 in the 7th loop of the condition 7. The conditions are generated and the signals of logical zero and logical unit are generated, respectively. They will allow the recording of a microcommand read by address C from the second memory block 4 to register 6, addresses B from output 13 of the second memory block 4 to the register of the first block 1 generating the address and address C to the register of the second block 2 generating the address from the output of its adder . If the condition oi is not fulfilled, then at the first 17 and second 18 outputs of the condition checker 7 there will remain signals of the logical unit and logical zero, respectively. They are allowed to write the value of the microcommand read from the first memory block 3 at address Bj, address B. - to the register of the first address generation block 1 from the output of its adder, zero address from the output 12 of the first memory block 3 to the register of the second block 2 address formation. Similarly, the device works when performing other microinstructions. In the table shown in FIG. 5, О, and 1 in the code field of the checked logical condition mean zero and one codes, respectively. The value of code O is used to write to the register 6 of the controlling part and the code of the checked logical condition of the next microcommand read from the first block 3 of memory, and the value 1 to write to the register 6 of the controlling part and the code of the checked logical condition of the next microcommand read from the second memory block 4. The use of these codes allows any firmware to be placed in blocks 3 and 4 of the device memory. Let us estimate the required total capacity of two memory blocks of the proposed device with respect to the required total capacity of two blocks of the known (Fig. 6 and 7) device. Suppose there are X operator vertices in the firmware located in two memory blocks, and conditional vertices. It should be borne in mind that microcommands that can be executed after conditional vertices are placed in the second memory block of a known device. Then the number of microinstructions located in the first memory block of the known device will be determined by the difference X-Y and, therefore, the required capacity of the first block is pa-. 7, m ti known device will be equal to this value. In the second memory block, the microinstructions are stored in Y, which is usually much smaller than XY, However, since the address values of microinstructions stored in the second memory block are determined by the address values of the corresponding microinstructions stored in the first memory block, the capacity of the second the memory block should be almost the same as the first one. As shown in FIG. 7, only two microcommands are stored in the second memory block, but they are not located at addresses B, B, but at addresses Bj and BZ and the capacity of the second memory block is therefore 6 cells, which can be considered approximately equal to the capacity of the first memory block ti. Thus, the total capacity of the two memory blocks of the Known y, device will be (X-Y) 2. In the proposed device, the total capacity of the two memory blocks will remain equal to X (Fig. 6). The total capacity of the two memory blocks in the proposed device will be less than in the known device K times, where K is defined by the ratio (X-Y) - 2 (1 -) 2. From the value - Ie. on the ratio of the number of conditional vertices to the number of operator vertices, the specific I value of K will depend on the implemented firmware. In FIG. 8 shows the dependence of K on - 100%. It can be seen from the graph that at values of -100% within 20-30%, the memory capacity when using the proposed device decreases 1.6-1.4 times as compared with the known device. And since the main expenses of the equipment when building firmware control devices go to the control memory, the application of the proposed device is more economical than the known device, while its speed will remain the same. Suppose that in the proposed and known devices the number of microcomms located in the second memory block is 2 times less than the number of microcommands located in the first memory block, then the length of the address field of microcommands located in the first memory block of the proposed device , less than the length of the address field of microinstructions located in the right memory block of the known device by m bits. With large volumes of the first memory block and small volumes of the second memory block, this fact also leads to a significant reduction in hardware.

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Claims (2)

1. A microcontroller control device comprising two memory blocks, microcommands, a switch, a microcommand register, and a condition checking unit, the microoperation code output of the microcommand register being the device output, a group of microcontrol register logic condition code outputs connected to the first group of inputs of the condition checking unit, the second group the inputs of which is a group of inputs of the logical conditions of the device, the information input of the micro-command register is connected to the output of the switch, the first and second information inputs which are connected respectively to the outputs of the operation codes and logical conditions of the first and second blocks of memory of the microcommands, the first and second outputs of the condition checking block are connected respectively to the first and second control inputs of the switch, characterized in that, in order to reduce equipment, it contains the first and the second. the second address generation units, the first and second control inputs of the first and second address generation units being connected respectively to the first and second outputs of the condition checking unit, the outputs of the first and second address generation units respectively connected with the address inputs of the first and second memory blocks of microinstructions, the address code which outputs connected respectively to the data inputs of the first and second address generation units. 2. The device pop. 1, characterized in that each of the address generation blocks contains a register, a switch, and an adder, wherein the register output is connected to the information input of the adder and is the output of the block, the information input of the register is connected to the output of the switch, the first and second control inputs of which are respectively the first and the second control inputs of the block, the first information input of the switch is connected to the output of the adder, the transfer input of which is connected to the unit potential bus, the second information input of the switch S THE information input unit. Λ> 1 1151962