SU1092514A1 - Device for correcting programs - Google Patents

Abstract

A DEVICE FOR PROGRAM CORRECTION, containing the first and second elements 2И-OR, typesetting command field, typesetting address field, buffer register-, register unit, and the output typesetting command field is connected to the information input of the register unit, the information output of which is connected to the first input of the second element 2I-OR, the output of which is the information output of the device, the information input of the device is connected to the second input of the second element 2I-OR, the output of the typed address field is connected to the first input of the first element 2 AND-OR, the output of which is connected to the information input of the buffer register, the address input of the device is connected to the second input of the first element 2И-OR, characterized in that, in order to improve speed, three elements NOT are entered into the device, three elements OR, two elements AND , a delay element, a write switch, two switches and an associative memory block, with the first 11 ICA. the contact of the first switch is athe /: s; 1c ;; and-en with the bus of zero potential, and its second contact is connected with the first input of the first OR element, with the in-switch of the recording switch, with the third input of the first element 2И-OR, the first input of the first element AND through the first element NOT with the first input of the second element OR, with the fourth input of the first element 2И-OR, with the input of the command field and the recording input of the associative memory block, the control outputs of which are connected to the control inputs of the record block of registers and with inputs of the third element nta OR, information input - with you (Buffer register stroke, the first and § second control inputs - with the outputs of the first OR element and the write switch, respectively, the first and second contacts of the second switch are connected respectively to the zero potential bus and through the second elec NOT with the write input of the write switch, with the second input of the first element OR, and through the delay element with the first input of the second element AND, the output of which is connected to the input of the read switch of the recording switch, the output of the third element OR of En with the second input of the first element AND through the third element NOT with the second input of the second element AND the second input of the second element OR, the output of which is connected to the third input of the second element 2I-OR, the output of the first element I connected to the fourth input of the second element 2, OR.

Description

The invention relates to computing and can be used to debug programs of digital computers operating in real time with programs that have a permanent storage device. A device for debugging programs is known that contains a block of registers, an address generation block, a control block, a storage device (an information device without information destruction, an instruction receiving and issuing unit, a persistent storage device ClT. A disadvantage of this device is low speed. A device for debugging is known programs, which contains a keyboard block, registers, operative one, a performer, and a C 2 drive. A disadvantage of this device is a large amount of additional equipment that is not always possible. Use in a digital computer at the place of its installation. The closest to the proposed is a memory with a program correction containing a control unit, a block of permanent memory, a register of the code of faulty addresses, an address and numeric registers, a register of the code of the initial state, a block of selections address, additional address register and control block, encoder, number selection block, semi-permanent memory block, four AND circuits, two circuits OR NW 3 The disadvantage of this device is the low speed in automatic correction mode program. The purpose of the invention is to increase the speed of the device. The goal is achieved by the fact that the device for correcting programs contains the first and second 2I-OR elements, the command dialing field, the address dialing field, the buffer register, the register block, and the output of the command dialing field is connected to the information input of the register block whose information output is connected with the first input of the second element 2I-OR, the output of which is the information output of the device, the information input of the device is connected to the second input of the second element 2I-OR, the output of the typed address field is connected to the first input of the first element 2I-OR, the output of which is connected to the information input of the buffer register, the address input of the device is connected to the second input of the first element 2I-OR, three NOT elements, three OR elements, two AND delay elements, a recording switch, two switches and an associative memory unit, the first contact of the first switch is connected to the zero potential bus, and its second contact is connected to the first input of the first element OR, to the input of the recording switch, to the third input of the first element 2I-IL , the first input of the first element AND and the first element NOT with the first input of the second element OR, with the fourth input of the first element 2И-OR, with the input of the command field and with the input of the block record. associative memory, the control outputs of which are connected to the control the write inputs of the register block and with the inputs of the third element OR, the information input with the output of the buffer register, the first and second control inputs with the outputs of the first OR element and the write switch, respectively, the first and second contacts of the second switch Ate connected respectively to the zero potential bus and through the second element NOT to the write input of the write switch, to the second input of the first OR element, and through the delay element to the first input of the second And element, the output of which is connected to the read input of the write switch commutator, the output of the third OR element connected to the second input of the first element AND through the third element NOT to the second input of the second element AND, the second input of the second OR element, the output of which is connected to the third input of the second element 2I-OR, the output of the first element And connected to the fourth input of the second OR-element 2I. FIG. 1 shows a block diagram of the proposed device; in fig. 2 is a block diagram of an associative memory block; FIG. 3 is a functional block diagram of an associative memory block; FIG. 4 is a functional diagram of a write switch. FIG. 1 shows the address register 1, the requesting device 2 programs, the command register 3, which are part of the digital computer, the device contains {FIG. 1) the first element 2I-OR 4, the first element is NOT 5, the second element is OR 6, the second element is 2I-OR 7, the first element is AND 8, the first switch is 9, the buffer register 10, the dial command field 11, the dial field 12 addresses, block 13 associative pazhiti, register unit 14, first element OR 15, write switch 16, second element NOT 17, delay element 18, second element AND 19, third element OR 20, third element NOT 21, second switch 22, Block 13 associative memory is a homogeneous two-dimensional structure of size, where n is the number of lines, and m is the number of one hundred lbtsov {figure 2} And with each of its element 23 contains (Fig. 3) the third element And 24, the first trigger 25, the fourth element And 26, the fourth element NOT 27, the fifth, the element And 28, the fourth element OR 29. Switch 16 the record contains (Fig. 4), n groups, each of which includes the second trigger 30 and the sixth element And 31, the seventh element And 32, the third trigger 33, the LED 34, The proposed device operates in the recording and correction modes. The write mode is set by closing the switch 9. In this case, the device operates autonomously and does not affect the operation of the digital computer. At the current address, register 1 from device 2 reads the next command, which through element 2И-И 7 with parallel code enters register 3, because at the input and, correspondingly, at the output, element OR b with the closed switch 9 is always found signal 1 and at the output of the AND 8 element is a signal O. The switch 9 also controls the element 2И-OR 4, which in recording mode skips the address of the register 10 only from the dialing field 12 the address. When the switch 9 is closed, the trigger 30 of the first group is set to one. 16 switch Records if the triggers 30 in all groups and the trigger 33 are in the zero state, and the signal through the OR element 15 arrives at the inputs of the elements AND 26 and 28 of all the elements 23 of the left column of block 13. This leads to the appearance of the signal O at the outputs of the elements OR 29 elements 23 of the right column of block 13, element 23 of which performs the function of one bit in a row, with the right column corresponding to the lowest bit and the left column to the most significant bit of block 13. The output from the HE element 5 opens the output of the command field 11 and allows operation of unit 13 in the mode e records received at input 24 of the AND element 23 of each block 13. Thus, after closing swi L 9 and flow transients ready to operate in the recording mode. On the address field 12, the address of the command written to the device 2 is set, which needs to be changed, and on the command field 1, the modified command code is set. At the same time, the address from the output of the dial-in field 12 of the address goes through the element 2I-OR 4 to the register 10. Shortly, the switch 22 closes. Signal 1 from the output of the element NOT 17 goes through the element OR 15 to the inputs of the elements AND 26 and 28 of all elements 23 of the left column unit 13, as well as the second inputs of the elements And 31 switch 16 records. The signal from the output of the element NOT 21 opens the element And 19, which also receives a signal from the delay ment element 18. The delay time is determined by the formula t.p-ln, (1). - the average signal delay time per element 23 of block 13, which is determined by the sum of the delays of the AND and OR elements entering into it; m is the number of elements 23 in the line of block 13. Thus, through time, from the output of the element And 19 The signal i goes to the third inputs of the elements And 31 of the switch 16 of the record. But only the trigger 30 of the first group, its output associated with the first input of the element And 31 of the first group of the switch. The 16 records are in the single state, therefore the signal from the output of the element And 31 enters the inputs of the element 1 and 24 of all elements 23 of the first row of the block 13, which also receives the address bit from the register 10, which is written to the corresponding trigger 25 of the element 23 lines of block 13. The trigger state 25 of element 23 of block 13 is compared with register 10; the unit is matched by AND 26, and zero by AND 28. The comparison starts from the left element 23 of the first row and ends at Signed out e of the OR element 29 of the right element 23 of the first line of block 13, according to which the command code 14 is written to the first register of the command code from the dialing field 11 commands and through the elements OR 20, NOT 21, AND 19, the AND element 31 of the first group of switch 16 records trigger 30 the second group is set to one state, and the trigger 30 of the first group is set to the zero state. Thus, the trigger 30 of the second group of the recording switch 16 corresponds to the first free line of the block 13 into which the next record can be made. When the switch 22y opens, the first inputs of all elements of the 23 left column of block 13 receive a signal. It calls a signal at the outputs of the elements OR 29 elements 23 of the right column of block 13. After dialing the next address on the dial 12, the address and command code on the dial 11 commands 11 hall switch 22 is closed and the write process is repeated, but only for the second line of block 13, and so on. At the same time, if the command code is corrected at the address already recorded in block 13, the address from register 10 is bitwise compared with all the lines of block 13 at the output of the OR element 29 in one of the elements of the right hand spider corresponding to the younger address signal. This signal highlights the line in which the address is stored, which coincides with the address on register 10, and also allows writing to the corresponding register of block 14 of the registers of the new command code. In this case, the input element And 19 receives the signal O, which prohibits the appearance at its output of signal 1 through t.-, and, therefore, the recording of the address from register 10 into the first free line of block 13. After the address is written to the last line of block 13, in the corresponding p-th group, trigger 30 of switch 16 of recording goes to the zero state, and trigger 33 into one state, which causes the LED 34 of the switch 16 to light up. New filling of block 13 is possible only after a general reset of all memory elements in block 13 (triggers 25) in switch 16 of the record (triggers 30 and trigger 33 and registers in block 14. Element 3 of the switch 16 records prevents even the appearance of a trigger signal) 30 of the first group of switch 16 of the record when Kscia repeatedly switches switch 9 if the block 13 is not completely filled. When the switch 9 is opened, the device switches to the correction mode. In this case, the input of element 2I-OR 4 connected to the output of register 1, opens and the entrance The output of the address dialing field 12 is closed.The address from register 1, except for device 2, is received by a parallel code through element 2I-OR 4 to register 10, and it goes to block 13. Signal O from the output of the element NOT 5 closes the output of dialing 11 commands and prohibits the recording of information in the rows of block 13. The signal from the output of the OR element 15 is fed to the inputs of elements VI 26 and 28 of all elements of the 23 left column of block 13, which allows searching by an associative attribute (address). When a match in one of the lines at the output of the element OR 29 of the element 23, corresponding to the lower bit of the line, a signal indicates that the address of the DVM program was found, by which the command code should be changed. The signal from the output of the element OR 20 through the element AND 8 and the signal O from the output of the element NOT 21 through the element OR 6 is fed to the element 2I-OR 7. The signal at the output of the element OR 29 of the element 23 corresponding to the youngest bit of the found line of block 13 is selected the register of block 14, the command code from which, through element 2I-OR 7, is written into register 3, and for device 2, element 2I-OR 7 is closed. Block 14 includes a group of registers, each of which uniquely corresponds to a row of block 13, and a switch that connects the selected register to the output of block 14. If the control outputs of block 13 have an O signal, then through element 2I-OR 7 to register 3 the command code from device 2 is recorded. Thus, in the program correction mode, the corresponding command codes of device 2 are automatically replaced with the modified command codes from block 14 of registers with minimum time. The technical and economic advantage of the proposed device lies in its higher speed in comparison with the prototype and in the exclusion of computer digital recordings when recording information; c1 program correction.

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Claims (1)

DEVICE FOR CORRECTION OF PROGRAMS, containing the first and second 2-OR elements, a typing command field, a typing address field, a buffer register ·, a register block, the output of the typing command field being connected to the information input of the register block, the information output of which is connected to the first input of the second element 2 AND-OR, the output of which is the information output of the device, the information input of the device is connected to the second input of the second 2-OR element, the output of the address field is connected to the first input of the first 2-OR element, the course of which is connected to the information input of the buffer register, the address input of the device is connected to the second input of the first 2I-OR element, characterized in that, in order to improve performance, three NOT elements, three OR elements, two AND elements, a delay element, a recording switch, two switches and an associative memory unit, the first contact of the first switch being connected to the zero potential bus, and its second contact being connected to the first input of the first OR element, with the second ed switch of the recording switch, with the third the course of the first element 2 AND-OR, the first input of the first element AND and through the first element NOT with the first input of the second element OR, with the fourth input of the first element 2 AND-OR, with the input of the typesetting command field and with the write input of the associative memory block, the control outputs of which are connected with the control inputs of the register block and the inputs of the third OR element, the information input with the output of the buffer register, the first and § second control inputs with the outputs] of the first OR element and the recording switch, respectively, the first and second the clocks of the second switch are connected respectively to the zero potential bus and through the second element NOT to the recording input of the recording switch, to the second input of the first OR element and through the delay element to the first input of the second AND element, the output of which is connected to the reading input of the recording switch, the output of the third OR element is connected with the second input of the first AND element and through the third element NOT - with the second input of the second AND element, the second input of the second OR element, the output of which is connected to the third input of the second element 2 AND-OR, the output first AND gate connected with the fourth input of the second OR-element 2I. SU, „, 1092514