SU1397922A1 - Device for shaping interrupt signal in program debugging - Google Patents

Abstract

The invention relates to computing and. can be used in a specialized computer control device to provide debugging programs. The goal is to increase speed. The device contains an interrupt trigger 1, which fixes the presence in the checked program of specified signs according to the selected mode of operation, the first - fourth elements are 2,4,8 and 9, the trigger 3 conditions fixing information 06 on the address finding condition in the specified area, switch 5, time selector 6 (second switch), a buffer register unit 7 for storing the sixteen last addresses of the commands executed until the moment of interruption, a masking unit 10 limiting the number of participants (O

Description

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in comparison of the information bits in accordance with the given mask information, the mode register 11, the first and second mask registers 12 and 13, the comparison block 14, the initial address register 15, the information register 16. In comparison with the known, the proposed device provides an increase in the performance of the debugging process of programs operating in real-time systems, for

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by introducing the first and second registers of the mask, information register, masking unit, time selector, trigger conditions, which provides the ability to select a test program, which is a small fragment in a complex set of programs running in real time, and check the progress of the processes according to specified featured, 1 Il.

The invention relates to computing techniques and can be used -jGEiano in a control unit of a single computer to enable debugging of programs.

The purpose of the invention is to increase speed.

The drawing shows a diagram of the device.

The device for generating an interrupt signal during the debugging of programs contains a trigger 1 interrupt, the first element AND 2, the trigger 3 conditions, the second element AND 4, the first 5 and second 6 switches, block 7 of the buffer registers, the third 8 and fourth 9 elements AND, block 10 masking, operating mode register 11, first 12 and second mask register 13, comparison block 14, starting address register 15, information register 16, clock 17 and setting 18 inputs, output of interruption 19, blocking input input 20, information output 21, input 22 sign of reading, input 23 of circulation B, inlet 24 signs conditional or unconditional jump, the input selector 25 of the operand address input 26 of feature command address, the first 27 and second 28 selection conditions input, input 29 of feature records information input 30 devices, the first 31 and second 32 vhbdy feature handling choice.

The device works as follows.

Four modes of operation are possible. The mode number is stored in a four-bit mode register 11.

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work, having both direct and inverse information outputs. Each register bit corresponds to a specific mode of the device. The selected mode of operation is determined by the presence of a unit in the corresponding register register.

In mode I, the device provides the formation of an interrupt signal when it hits a specified command address or a specified program address area (one in zero de reg).

In mode II, the device provides for the formation of an interrupt signal when executing, in a given program, commands for conditional or unconditional jumps to a given (forbidden) address range (unit 6 of the first digit of the register).

In mode III, the device provides for the formation of an interrupt signal when commands are executed in a given area of a program that circulate (read or write) to the specified (forbidden) region of memory addresses (a unit in the second decimal register).

In IV mode, the device generates an interrupt signal when executing commands that write the specified information or a part of it to a certain area of addresses of memory cells (one in the third bit of the register).

Thus, the device generates an interrupt signal in modes II, III and IV. npH coincidence of two signs, in mode I - one. In mode I

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The feature is the specified program area. In modes II and III, the first sign is the specified area of the program, the second sign is the specified (forbidden) area of jump addresses or the specified area of addresses of calls. In mode IV, the first sign is the specified area of memory addresses, the second is the specified area of recorded information. The address area or information area is specified using one pair of registers. In the first register, the starting address or information of the region is indicated, in the second - the mask information, which determines which bits of the comparison result to block and which to allow. Thus, the first sign is determined by the information of a pair of registers 12 and 15, and the second sign is determined by the information of a pair of registers 13 and 16. Registers 12, 13, 15 and 16 are implemented on

circuits with a tristable state - 25 inputs of the fourth element And 9, and knowledge of information outputs or outputs with an open collector, with the aim of providing the possibility of bitwise combining to implement the OR function.

Comparison unit 14 is designed for dp of comparison of two information streams, arriving respectively from information inputs 30 of the device and from the combined outputs of the register of the initial address and the information register. The result of the comparison passes through a masking unit 10, in which, according to the mask information of the register 12 or register 13, a certain part of the bits can be blocked. Further, the fourth element And 9 produces the formation of the evaluation signal of the result of the comparison over all bits of the compared information flows. This signal can be recorded as the first sign in the trigger 3 conditions or as the second sign fixed in the trigger 1 interrupt when the first is present, which is provided by the first element AND 2, the control of the first 5 and second 6 switches, which provide connection of the necessary information and control signals to the flip-flops, carried out by signals from the outputs of the register I mode, with direct and inverse connected to the first switch 5

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the outputs of the third bit, and to the second switch 6, the direct outputs of the zero, first, second, and third bits of the register.

Thus, in mode I, the instruction address or the starting address of the program area is recorded in the starting address register 15. Record in the register of the start address, as well as in the first, second mask registers, or the information register is made by submitting information to the information input 30 of the device, corresponding to (the signal of the input to input 32 or

27, 31 or 28 and the signal recording in the registers at the input 29 of the device. In the first mask register 12, the mask information is recorded. Each bit of the register of the initial address corresponds to the bit of the first mask register so that the presence of units in the last one does not mask by block 10 the results of the comparison in the given frame rate.

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Zero is forbidden. Thus, by writing zeros to the lower bits of the first register of the 12 mask, you can set the address area equal to Q 2, where n is the number of written zeros, starting with the lowest bit. In the limiting case, when p 0, a specific address is given, the coma IDE,; a program stage at which the interrupt signal is generated. The zero-bit output of register 11 of the operating mode blocks the output signal of the second switch 6, setting its value to one, and the unit on the I {top output of the third bit switches the information from the input 26 of the device command address sign to the output of the first switch 5. information inputs 30 of the command address information device is accompanied by the appearance of a signal at the device input 26, which, coming from the output of the first switch 5 to the sample inputs of registers 12, 13, 15 and 16, causes the connection of information from the outputs of the register 15 of the starting address and from the outputs of the first register 12 of the mask to the second inputs, respectively, of the comparator unit 14 and the masking unit 10.

The signal from the output of the fourth element And 9, reflecting the result of a comparison of the address information performed

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kimlndy with a given area of the world., switches through the second element AND 4 and is recorded in the trig p 3 conditions. The information from the forward exit of trigger 3 conditions, the passage through the first element I 2, is rewritten into trigger 1 interrupt. In the case of a comparison, the trigger 1 interrupt goes into one state and the latch-10 address and the first register 12

replies, fixing the interrupt signal at the output 19 of the device. At the same time, the interrupt signal arrives at the first input of the third element AND 8, blocking the recording of the addresses of the commands being executed in block 7 of the buffer registers. Thus, the storage of the last addresses of the executed commands is provided until the moment of interruption. The soder-jfaiMoe of block 7 buffer registers can be overwritten into the main memory of the interrupt processing program for the subsequent program analysis by the programmer. Selection of information and recorded the last sixteen addresses of commands executed from block 7 of the buffer registers to the information output 21 of the device is performed sequentially by applying a read signal to the input 22 of the device.

In II, in the register 15 of the starting address and in the first register 12 of the mask, the address area of the program to be checked is specified, and in the information register 16 and in the second register 13 of the mask, the forbidden address area for conditional or unconditional jumps is specified.

In mode IV, in the register 15 of the start address and in the first register 12 of the mask, the addresses of the memory cells are specified, and in register 16 of the information and in the second register 13 of the mask, the information whose entry is prohibited to 30 in the specified area is specified. The operation of the device in mode IV is similar to its operation in modes II and III, with the exception of the operation of the first 5 and second 6 switches. The first switch 1 in this mode switches the signal from the input 25 of the devices to the input of the second element AND 4. Thus, the trigger 3 conditions fixes the result of the comparison of the current

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Similarly, as in the mode, the trigger 3 conditions captures the result of the address at which the growth of the address information is processed, with the specified address area of the command with the specified address area of the program. However, the information from the direct output of the trigger 3 conditions to the second input of the first element I 2 acts as a necessary condition for recording information from the output of the second switch 6 to the trigger 1 interrupt, and not unconditionally overwrites the last one. The second switch 6 commutes to its output a signal from the output of the fourth element And 9, reflecting the result of comparing the formed address of the conditional or unconditional transition

owls The second switch 6 provides the switching of the comparison result signal from the output of the fourth element AND 9 to the input of the first element AND 2 in the presence of a signal at the input 23 of the device.

Claims (1)

Invention Formula 50 55 A device for generating an interrupt signal during program debugging, containing an interrupt trigger, a block of buffer registers, a comparison block and a starting address register, the interrupt trigger output and the group of outputs of the buffer register block are respectively the interrupt outputs and the information output group of device 30 inputs. a given region of addresses of transitions at the time of the presence of a signal at the input 24 of the device. In the case of comparison at the output of the second switch 6, a single signal is generated, which, through the first element I 2, when one of the conditions is met, triggers trigger 1 and causes the formation of an interrupt signal at the output 19 of the device. In mode III in the register 15 0 j. the mask specifies the address area of the program being scanned, and in the information register 16 and the second register 13 of the mask, the forbidden area of addresses of the memory cells. The operation of the device in mode III is similar to the operation of the device in mode II. An exception is the operation of the second switch 6, which provides the switching of the signal of the result of the comparison with the output of the fourth element 9 at the first input of the first element 2 when there is a signal at the input 25 of the device. In mode IV, in the register 15 of the start address and in the first register 12 of the mask, the addresses of the memory cells are specified, and in register 16 of the information and in the second register 13 of the mask, the information whose entry is not allowed in the specified area is specified. The operation of the device in mode IV is similar to its operation in modes II and III, with the exception of the operation of the first 5 and second 6 switches. The first switch 1 in this mode switches the signal from the input 25 of the device to the input of the second element AND 4. Thus, the trigger 3 conditions fixes the result of the comparison of the current five n the address at which the call is made, with a given address area address at which a call is made with a given address area owls The second switch 6 provides the switching of the comparison result signal from the output of the fourth element AND 9 to the input of the first element AND 2 in the presence of a signal at the input 23 of the device. Invention Formula address at which a call is made with a given address area A device for generating an interrupt signal during debugging of programs containing an interrupt trigger, a block of buffer registers, a comparison block and a starting address register, the interrupt trigger output and the group of outputs of the buffer register block are respectively the interrupt outputs and the information output group of the device, the information, 1 and device input connected to the information input of the register of the initial address, the output of which is connected to the first input of the comparison unit, characterized in that, in order to increase the speed In the device, four elements And, the condition trigger, the first and second switches, the masking unit, the operation mode register, the first and second mask registers and the information register are entered, the clock input of the device is connected to the synchronization inputs of the interrupt triggers and the trigger condition connected to the first input of the first element I, the input of the initial installation of the device is connected to the zero installation inputs of the interrupt trigger and the conditions trigger, the input of the sign of the device operand address selection is connected to ne By the first control inputs of the first and second switches, the output of the first switch is connected to the first input of the second element I, the read inputs of the first mask register and the initial address register, and the read blocking inputs of the second mask register and information register, the input of the command address attribute of the device connected to the second control the input of the first switch and the first input of the third element I, the first and second inputs of the device condition selection are connected to the recording inputs of the first and second mask registers respectively; mark recording device connected to the clock inputs of the first and second mask register, the start address register and the register information, the group information input apparatus connected to the groups of information inputs of the first and second PE; mask mask, second group of inputs 0 five the comparison unit, the group of information inputs of the information register and the block of buffer registers, the group of bit outputs of the first and second mask registers are connected to the first group of information inputs of the masking unit, the output group of which is connected to the input group of the fourth element And, the group of information register outputs is connected to the first group the inputs of the comparison unit, the output group of which is connected to the second group of inputs of the masking unit, the output of the fourth element AND is connected to the second input of the second element AND and the second control input of the second commutator, the output of which is connected to the second input of the first element H, the direct and inverse outputs of the third section of the mode register are connected to the information inputs of the first switch, the direct outputs of the bits from zero to the third mode register are connected to information the inputs of the second switch, the outputs of the first and second elementals And are connected to the information inputs, respectively, of the condition and interrupt triggers, the inputs of the transition signs and the device write access are connected according to With the third and fourth control inputs of the second switch, the output of the interrupt trigger is connected to the second input of the third element I, the output of which is connected to the write input of the buffer register block, the read indication of the device is connected to the read input of the block of buffer Q registers, the lock input sign of the device is connected the interrupt trigger interrupt input, the first and second inputs of the device selection feature tags are connected to the recording inputs of the registers, respectively five 0 five five information and starting address.