SU1339559A2 - Control device - Google Patents

Abstract

The invention relates to computing and can be used in information processing for coordinate-sign and television indicators, as well as in other cases when information must be arranged in accordance with its changes. The aim of the invention is to expand the field of application of the device by realizing the possibility of analyzing the input data for identity. The device contains (/) С ОО со со э or СЛ СО Гч

Description

five registers 1-5, two counters 6-7, comparator 8, three switches 9-11., memory blocks 12, control 13 and identification 14. The identification unit is activated by the device based on the recording of new data into the array of displayed information. Together with the comparator, the identification block provides a comparison of specified

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The invention relates to computing, can be used in the processing of information for coordinate-sign and television indicators, as well as in other cases where it is necessary to arrange the information in accordance with its changes, and is an improvement of the device according to the main author. St. № 1 171790.

The purpose of the invention is to expand the scope of application due to the possibility of anapiz input data for identity.

FIG. 1 shows a block diagram of the device; in fig. 2 - an embodiment of the identification block; FIG. 3 is a timing diagram of the operation of the identification block in FIG. 4 is a diagram of the connections of the device with the known; in fig. 5 a, b, c - the algorithm of the device in the recording and erasing modes; in fig. 6 - erase algorithm,

The device (Fig. 1) contains registers 1-5, counters 6 and 7, a comparator 8, a data switch 9, an address switch 10, a switch 11, a memory block 12, a control block 13, and an identification block 14.

The component parts of the device are interconnected with external devices (data source and indicator) connections 15-56.

The identification block (Fig. 2) contains the fourth pulse distributor 57, the switch 58 pulses, the fourteenth through sixteen triggers 59-62, the twenty-third through the thirtieth elements And 63-70, the seventh number of characteristics of the newly entered data with those in the array. When the identification conditions are fulfilled, the identification unit provides the device with the implementation of the erase operations at the beginning, and then entering new data. The identification block does not affect the operation of the device in the modes of erasing and reading data. 6 Il.

th to fourteenth elements OR 71-78, elements 79-81 of delay.

The pulse distributor 57 is similar to the distributors used in the other blocks of the basic invention. Switch 58 is implemented on microchips 533ID4.

The device operates as follows. If there is no signal, the Record Sign (PZ) trigger 59 is in the reset state. Therefore, the switch 58 by the signal from the inverse output of the trigger 59 provides the signal flow equal to () from the input

the unit (one of bus 47) directly to its output (one of bus 46), and the signals More () and Strobe Comparator (CK) from the input of the block (bus 47 and 19) to its output (bus 46 and 48 ) through the elements OR 75 and 77, respectively. The Ready signal of the receiver (GP) passes from the block input (bus 42) to its output (one of 5 tires 30) through an element 67, the output of which is allowed by a signal from the inverse output of the trigger 61, which is in a reset state. The End of Transmission (KP) signal from the block input (bus-0 to 33) passes to its output (bus 41) through the element OR 76. Thus, in the absence of a PZ sign, the identification unit 14 broadcasts the signals arriving at the inputs and does not influence on the operation of the device as a whole.

The PZ signal switches the trigger 59, which controls the switch 58 and permits the passage of signals. The higher bits are equal (MFR) through the elec

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cops AND 63, OR 72 at the input of the distributor 57 in the presence of permitting signals of the signs of coordinates (PCC and PKU), coming through the buses 51 at the input of the element And 63 from the element OR 71. If the input of block 14 is approached by two

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signal CTP, referring to one file, then the distributor 57 at the first output generates a signal that sets the trigger 60. The signal from the output of this trigger allows the signals, from the input of the block (bus 47) to pass through the switch 58 to the inputs of the And 64 and 65 circuits. If a specified number of signals corresponding to the number of identifiable characteristics of an object arrive at the input of block 14 within one file, then at the second output of the distributor, an identification signal is formed, which, passing through the OR 74 elements and delays 79, resets the trigger 60 and valve 57, sets the trigger 61 and through the element OR 75 enters the outputs of the block as a signal. The signal arriving at the block input via bus 45 The end of write-erase (GLC) passes through elements AND 69, delays 81, PfflH 76 to the output of the block as a signal KP (bus 41); the same signal from the output of the element AND 69 through the elements OR 78 and the delay 80 causes all the triggers of the block to be reset.

Signals or, which from the switch output go to the inputs of the OR element 73, reset the trigger 60 and the distributor 57 through the elements AND 65, OR 74 and the delay 79 only if the trigger 60 is in the cocked state ( comparing coordinates). The distributor 57 is also reset by the SP signal through the elements AND 66, OR 74 and the delay 79 (incomparison of one of the coordinates),

When the identification unit is put into operation as an SC signal, the read register 1 (FPS 1) signal is used, which from the bus 50 through the switch 58 and the element OR 77 enters the output of the block (bus 48).

The signal End of the array (KM), post 55 on one of the tires 18 - signal recording on

 to the input of the block via the bus 43, in the mode of operation of the block 14 is fed to the C input of the trigger 62, which together with the element And 70 implements the function

register 3.. As a result, the address of the first word of the array is written into register 3. Then, using the signals from block 13 on buses 18 and 24, the code from register 3 is entered

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the selection of each second signal KM, coming from the output of the element AND 70 through the elements OR 78 and the delay 80 to reset all the triggers of block 14.

All triggers are reset and block 14 is also turned off by the CTP signal relative to any of the coordinates, via AND 68, OR 78 and delay 80.

The comparator 8 is implemented on microcircuits 533 SP1 with a separate output of the Equals, More and Less signals for higher bits. The remaining units of the device are left unchanged and are described in the basic invention.

The array of displayed data stored in block 12 consists of M files, each of which includes k words each and contains all information about a single displayed object (its number, coordinates, and other characteristics). In addition, at the end of each file there is one service word containing information about the address of the first word of the subsequent file (address word). Thus, the entire array of displayed data is a sequential chain of object data. Q files associated with each other in accordance with the ordering law. Each address word contains a unit in an extra bit (address sign). Addresses of adjacent words in the file differ by one.

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The device can operate in the modes of periodic issuance (regeneration) of data on the indicator; records of newly received data with the implementation of the identification of the displayed data with the newly entered data; erase obsolete data.

When the power supply voltage is turned on, all elements of the device memory are reset.

Recording mode (Fig. 5).

In the counter 7 in the initial state, the code 0 ... 0 is set, which corresponds to the starting address of block 12, which stores the first address of the first word of the array of displayed data. From the control unit 13, one of the busses 16 reads the signal Read, and

register 3.. As a result, the address of the first word of the array is written into register 3. Then, using the signals from block 13 on buses 18 and 24, the code from register 3 is entered into 5

 It is located in counter 7 through switch 10. Thus, in counter 7, the code of the address of the first word of the array is set.

According to the read and write signals on buses 16 and 17 from block 13, the data of one file successively rewritten word by word from block 12 to register 2 via buses 22. To do this, by a signal on bus 29 from block 13, the address code in counter 7 is increased by 1, At the same time, the code from the output of block 12 goes through tires 22 to one of the inputs of block 13, which, on the basis of the address word, generates a write signal on one and the tires 18, using which the address code of the first word of the next file is entered into register 3. After that, the unit 13 sets on the bus 31, the signal readiness of the device to transfer (GUL). In response to it, readiness and reception signals (HIP) n transfer control (TUI) signals are received from the indicator on the device buses 32, using which the unit 13 generates a control signal of the transfer device (TSD) on one of the buses 31 and a read signal of the register 2 on one of the buses 17. The code readable from register 2 is transmitted to the indicator through the buses 56 of the device. The process continues until the completion of the transfer to the single file inidkator, and the register 2 generates the last word sign (PPP) signal, which via bus 21 goes to block 13.

The signal of the PPP unit 13 on one of the tires 31 generates a signal of the end of the transmission device (KPU). Then, from the memory block 12, the words of the next file are copied to register 2, which are then transmitted to the indicator, and the described process repeats until filling on the buses 22 in the address word of the zero code, using which the block 13 on the bus 43 generates the array end signal (CM ). This signal starts a new array reading cycle. Simultaneously with reading (regeneration) of data on the indicator, block 13 analyzes the signals arriving at its input via buses 33 from the source of the displayed data.

Recording mode

The recording of newly received data, taking into account the identification operations, is carried out as follows. Control unit 13 is exchanged with the source.

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data signals on the buses 30 and 33 about the readiness to receive and transmit data and buses AO devices set data codes, which signals on the bus 49 are sequentially entered into the register 1. After the transfer of the last word of the file on one of the SRI 33 signal 10 KP, which is transmitted through block 14 via bus 41 to block 13.

On one of the tires 40 from the data source, the control unit 13 receives a PZ signal, which, via the bus 44

15 enters unit 14, including it in operation. If there is no PZ signal, then the incoming data refers to the file to be erased and is used to search it in the array.

20 According to the first signal KM, which arrives after the signal KP, block 13 forms on one of the buses 50 a signal FRP 1, which also goes to block 14 and is used to form the signal SC. Codes from register 1 are read simultaneously with reading data from block 12 and written to register 2, the code from register 1 output goes to comparator 8,

30 to the other inputs of which codes are received with i1in 22., read from block 12. In response to the signals from the IC, coming from block 14 via bus 48, the comparator 8 generates signals More

35 (), Less (s), Equal To (), Higher Senior Units (CTP) Less Senior Units (-iCTP) Equal Higher Units (CTP), which for buses 47 go to block 14, Comparison number 8 compared by 8

most significant bits correspond to a given otd zone; If in the same file, block 14 receives two CTP signals, where they are gated with the prizes of the coordinates of the PCC, the PCB from bus 51, this indicates the possibility of identifying the newly entered file with the one in the array. Further comparison of object characteristics is carried out over the full number of bits (the signal from comparator 8 is used). If the codes of a given number of characteristics coincide, the search for a volume that is identical again

gg is entered, terminated, and this means that its corresponding file should be removed from the array of displayed data. Therefore, block 14 on one of the tires 46 generates a signal

which enters the block 13 and forms the formation of the signal End of Search Operations (COP). In this case, the output of block 14 associated with bus 20 does not have a PZ signal, which corresponds to the device’s implementation of the erase mode, which is described below,

After completion of the erase operation; Neither block 13 generates the signal End of write-erase (GLC), which enters block 14 via bus 45. Block 14 is disconnected from this signal, a PZ signal is generated and a signal KP is simulated, which passes through bus 41 block 13. To exclude the display of the GP signal to an external device and the possibility of establishing a connection with it before completing the recording procedures, block 14 prohibits this signal for the time between the beginning of the GLC signals and the simulated transmission.

Identification operations performed by .block 14 can be interrupted within the same file by the i-gctr signals. These procedures will be continued during the other file until an identifiable object is found or a CTP or CM signal is generated. In any of these cases, block 14 is turned off and a PZ signal is generated, which causes the device to continue to operate in recording mode.

The write mode begins with the procedures for finding the location of the input data in the array. These data are in register 1. The codes read from register 1 simultaneously with the codes from the output of block 12 are sent to a comparator 8, the output signals of which, and through block 14, enter block 13. The signal SC in this case is formed in block 13 for signs of the PCH, PKU only for the coordinates and through the block 14 is transmitted to the comparator 8.

According to the signals generated by block 13 on buses 16, 18, 36 and 23, the codes of addresses of the first words of the files are written to register 3 from the output of block 12, and the codes of addresses of the last words of files from counter 7 through buses 35 are fed to the input of switch 11, and then, buses 34 are written to register 5. Register 5 contains codes for the addresses of the last words of two files: files, the reading of which from block 12 is completed and the previous one. Described actions

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and initiate- continue operations.

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search, i.e. before the arrival of the CPC signal. A CPC signal is generated by block 13 in the event that comparator 8 receives either two signals from one file or one signal. After the passage of the signal, the CPC unit 13 stops forming the reading signals of register 1 and writing the addresses to register 5, in which the addresses of the last words of those files between which the newly entered file should be placed and whose data is stored in register 1, will be written.

The addresses of the memory 12 that are necessary for writing a new file can be obtained in two ways - either from counter 6, which stores the value of the last free address of block 12, previously not used, or from register 4, which stores the address of the first word of the free address group, on which previously displayed data were stored, and then were erased. Such groups of free addresses also form an array of free addresses, linked in groups along a chain, similar to an array of displayed data. The zero value of the code in register 4 o starts the absence of an array of free addresses, in this case they are determined only by the counter 6. In the device operation process, to enter new data, the addresses of the array of free addresses are used first. The free addresses from counter 6 are taken only if they are not in the array of free addresses.

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In the presence of single values of the signals of the CPC from the PZ unit 13 generates a sequence of signals on the tires 23, 24, 16 and 36, providing reading of the register 5 and passing

45 through the switch 10 to the counter 7 on buses 54 of the address of the last word of the previous file, read from block 12 the code of the address of the first word of the subsequent file and write it to the register of the 5 through the switch 11 on buses 34. Let us read the control signals on the tires 37 Register 4 enters bus 13 through bus 38 and is analyzed there. If the code is in the register

55 4 zero, the free addresses of the block 12 for recording new data are determined by the counter 6, which is initially set to the state corresponding to the maximum number of words of the block

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search, i.e. before the arrival of the CPC signal. A CPC signal is generated by block 13 in the event that comparator 8 receives either two signals related to one file or a signal. After the passage of the signal, the CPC unit 13 stops forming the reading signals of register 1 and writing the addresses to register 5, in which the addresses of the last words of those files between which the newly entered file should be placed and whose data is stored in register 1, will be written.

The addresses of the memory block 12 necessary for recording a new file can be obtained in two ways - either from counter 6, which stores the value of the last free address of block 12, previously not used, or from register 4, which stores the address of the first word of the group of free addresses where Previously stored data is displayed, and then were erased. Such groups of free addresses also form an array of free addresses, linked in groups along a chain, similar to an array of displayed data. The zero value of the code in register 4 means the absence of an array of free addresses, in this case they are determined only by the counter 6. During operation, the device for entering new data primarily uses the addresses of the array of free addresses. Their free addresses from counter 6 are taken only if they are not in the array of free addresses.

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In the presence of single values of the signals of the CPC from the PZ unit 13 generates a sequence of signals on the tires 23, 24, 16 and 36, providing reading of the register 5 and passing

45 through switch 10 to counter 7 via buses 54 of the address of the last word of the preceding file, reading from block 12 of the code of the address of the first word of the subsequent file and writing it to the register of the 5 through switch 11 via buses 34. Let us read the contents of the control signals on the tires 37 register 4 via bus 38 enters block 13 and is analyzed there. If the code is in the register

55 4 zero, the free addresses of the block 12 for recording new data are determined by the counter 6, which is initially set to the state corresponding to the maximum number of words of the block

12 minus one. In this case, the code from the output of counter 6, via a signal on buses 25 and 26, passes through switch 9 to the information inputs of block 1 2 and is written to it at the address of the last word of the previous file set in counter 7. Then the same first address of the newly entered file through the switch 10 (control on one of the buses 24 from block 13) sets the counter 7. Next, the signals from the e-block 13 on the buses 29, 25, 1.6 and 50 provide a change of 1 in the counter 7, decrement by 1 the address code in counter 6, writing new data to block 12 from register 1 to bus 39 via switch 9. By the PPP signal generated on bus 52 by register 1, complete- 20 - Read operation written to block in this address 12th dan from block 12 the address of the first word of the file- According to the signal of PPP

new file. But the signal lUiU from block 13 to block 12 is given a signal of the address word of the record and the address of the first word of the subsequent file from the output of register 5 via buses 27 via switch 9.

If the code from register 4 has a non-zero value, then block 13 generates control signals on buses 37 and 26, through which the code from the output of register 4 passes through switch 9 and is recorded as previously set in counter 7. Then data from register 1 written to block 12 in the same way as described above (counter 6 in this case does not receive a signal), the address from the last (address) word reads information from block 12 and the first address of the next free group of cells of memory 12 is written to register 4 by the control signal on the bus 37. perazim recording mode in this case are completed input unit 12 to set the counter 7 at last elo-- va file newly introduced subsequent address of the first word from the register file 5 through a switch 9.

The GLC signal generated by block 13 after completion of write operations is transmitted by block 14 back to block 13. The signal from block 13 via bus 41 enters block 14, from where bus 30 is transmitted to the data source to signal that the device is ready to receive new data.

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next to the erasure, is entered into the register 5 through the switch 11 via the control signal on one of the buses 36 from block 13. Next, the signal on one of the buses 37 reads the register 4 and through the switch 9 in block 12 enters the code of the address of the first cell of the group free cells From the register 5, the code of the address of the last word of the file preceding the erased is read, and through the switch 10 is entered into the counter 7. At the address specified in the counter 7, the information from the block 12 is written to the address 4 of the address of the first word to be erased. file, which now becomes the first address of the array of free cells of block 12.

The erase operation is completed by reading from register 5 the address of the first word of the file following the erase, and its introduction to block 12 via switch 9 at the address previously set in counter 7.

After completion of the erase operation by the unit 13, the GLC signal is generated on the bus 45, and the main signal is also set and the regeneration data continues.

The proposed technical solution, in comparison with the known, provides an extension of the functionality of the device, since in addition to the ordering and regeneration of information for the indicator, it allows to identify data about the displayed objects, and the identification operations are realized during the display

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Erase mode (Fig. 6).

The deletion of obsolete data is carried out as follows. The search for the file whose data is to be erased from the memory unit 12 is implemented in the same way as the above search in the write mode. As a result, search operations in register 5 will store the addresses of the last words of the files, one of which precedes the erasable one, and the other follows it.

The inclusion of an erasable file into an array of free addresses is implemented using the following operations. The address code of the last word of the erasable file from register 5 through the switch 10 is entered into counter 7 with control signals from block 13 on buses

0 - The address of the first word of the file read at this address from block 12

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next to the erasure, is entered into the register 5 through the switch 11 via the control signal on one of the buses 36 from block 13. Next, the signal on one of the buses 37 reads the register 4 and through the switch 9 in block 12 enters the code of the address of the first cell of the group free cells From the register 5, the code of the address of the last word of the file preceding the one to be erased is read, and through the switch 10 is entered into the counter 7. At the address specified in the counter 7, the information from the block 12 is written to the register. 4 addresses of the first word erasable. file, which now becomes the first address of the array of free cells of block 12.

The erase operation is completed by reading from register 5 the address of the first word of the file following the erase, and its introduction to block 12 via switch 9 at the address previously set in counter 7.

After completion of the erase operation by the unit 13, the GLC signal is generated on the bus 45, and also the HH signal is set and the data regeneration continues.

The proposed technical solution, in comparison with the known, provides an extension of the functionality of the device, since in addition to the ordering and regeneration of information for the indicator, it allows to identify data about the displayed objects, and the identification operations are realized during the display

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111339559

information with minimal time costs.

Identification of information is implemented on specialized VMs. In the proposed device, these tasks are solved due to the insignificant hardware complexity of the device. Due to this, the time of a specialized computer can be used to solve other tasks of an automated control system, i.e. l increase its efficiency, which is especially important when working in real time.

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Claims (1)

Invention Formula Control device auth. St. No. 1171790, referring to the fact that, in order to expand the scope of application due to the possibility of analyzing the input data for identity, it additionally introduced a pulse switch, the fourth pulse distributor, the third counter, from the fourteenth to the sixteenth triggers, from the seventh to fourteenth elements OR, from the twenty-third to the thirtieth elements And, from the fourth to the sixth elements of the delay, and the output of the sign of the X coordinate and the output of the sign of the coordinate Y of the first register are connected respectively to the first and second inputs The seventh OR element, the output of which is connected to the first inputs of the twenty-third, twenty-sixth and twenty-eighth elements, AND, the output of the eighteenth element, AND, is connected to the installation input to 1st of the fourteenth trigger, the direct output of which is connected to the second input of the twenty-third element, And output which is connected to the first input of the eighth element And, the output of which is connected to the clock input of the fourth pulse distributor, the first output of which is connected to the input of the installation of 1 to the fifteenth three hera, the direct output of which The first is connected by the first inputs of the twenty fifth and twenty fourth elements AND, the output Equals the Elder bits of the comparator connected to the third input of the twenty third element AND, the outputs of the Major and Minor bits of the comparator are connected respectively to the second and inputs of the twenty sixth and twenty eighth elements AND , direct and inverse four-outs 12 0 0 five 0 five 0 That trigger is connected to the control inputs of the pulse switch, the outputs Equal To, More and Less than the comparator are connected respectively to the first, second and third information inputs of the switch. Pulses, from the first to the seventh outputs of which are connected respectively to the second input of the twenty fourth element And, to the synchronization input of the eighth trigger, to the first input of the ninth element OR, to the first input of the eleventh element OR, to the 5th second input of the ninth element OR, to the first and second inputs of the thirteenth element OR, whose code is connected to the comparator gating input, the eighth output of the pulse switch is connected to the first input of the thirtieth element And and to the counting input of the third counter, the overflow output of which is connected to the second input of the thirtieth element And, the output of which is connected to the installation input of trigger and with the input of the fifth delay element, the output of which is connected to the first input of the tenth OR element, with the installation input into the third counter of the fourteenth, sixteenth and sixteenth triggers, the output of the sixth element AND with connected to the fourth pulse switch input, the output of the fourth element OR is connected to the fifth information input of the pulse switch, the output of the fourteenth element AND is connected to the sixth information input of the pulse switch, the output of the ninth element OR is connected to the second input of the twenty fifth element I, the output of which is connected with the second input of the tenth OR element, the output of which is connected to the input of the fourth delay element, the output of which is connected to the reset input of the fourth pulse distributor and the input of In the Fifteenth trigger, the output of the twenty-sixth element AND is connected to the third input of the tenth OR element, the output of the twenty-fourth element AND is connected to the second input of the eighth element OR, the second output of the fourth pulse distributor is connected to the fourth input of the tenth five 0 five element OR, with the input of the installation in 1 of the sixteenth trigger, with the second input of the eleventh element OR, the output of which is connected to the first input the house of the fourth element OR, the output of the twenty-eighth element AND is connected to the second input of the fourteenth element OR, the direct output of the sixteenth trigger is connected to the first input of the twenty-nineth element AND whose output is connected to the third input of the fourteenth element OR and which is connected to the first input of the twelfth element OR, the output of which is connected to the installation input in About the first trigger, the output of the fifth element OR is connected to the second input of the twenty-ninth element AND, the inverse output of the sixteenth trigger is connected to the first input of the twenty-seventh element AND, whose bbc is connected to the output of the transmission readiness of the device the input of the twenty-seventh element AND, the input of the end of the device transfer is connected to the second input of the twelfth element OR. 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