SU1520533A1 - Electronic computer - Google Patents

Abstract

The invention relates to computing and can be used in control systems. The purpose of the invention is to increase the productivity in processing the bowl data structures. The computer contains processor 1, memory block 2, input / output unit 3, list processing node 4, reset input 5, synchronization inputs 6 and 7, information output 8 and input 9, control outputs 10 and 11, control inputs 12 and 13. At the first stage, processor 1 prepares the initial parameters in block 2 of memory, which determine the execution of certain procedures with lists of data. At the second stage, the list processing unit 4 directly performs the required procedure using previously prepared parameters. 7 ill., 7 tab.

Description

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The invention relates to computing and can be used in control systems.

The purpose of the invention is to improve the performance of computers when processing list data structures.

Figure 1 shows a diagram of a computer; figure 2 - diagram of the processing unit lists; figs - 5 - timing charts of the computer; Fig. 6 shows the structure of the list; Fig. 7 shows a diagram for performing an operation with a list.

The computer (FIG.) Contains a processor 1, a block 2 of memory, a block 3 of input-output, a node 4 for processing lists. The computer has a reset input 5, synchronization inputs 6 and 7, information outputs 8 and input 9, control inputs 10 and 11, control inputs 12 and 13,

The list processing unit 4 (FIG. 2) contains a parameter memory block 14, an operand memory block 15, information registers 16 and 17, address counters 18 and 19, an adder 20, a block 21 comparison

address multiplexer 22 addresses, address decoders 23 and 24, microinstructions memory block 25 operations register 26, microinstruction addresses register 27, conditions multiplexer 28, control decoders 29-31, bus switches 32-34, bus drivers 35-39, control trigger register 40 trigger 41 states, capture trigger 42, interrupt trigger 43, AND elements 44 and 45, OR elements 46 and 47.

On the timing diagrams of the microcomputer (Fig.3-5) indicated: 48 - pulses at the inputs 6 and 7 of the synchronization of the computer; 49 - signal at the address output of processor 1; 50 - signal data on the information input-output processor 1; 5 and 52 are the signals at the read and write inputs of memory 2, respectively; 53 - signal to the control output of the processor 1; 54 and 55 are the signals at the capture confirmation input and the microprocessor confirmation output 1, respectively; 56 - the signal at the output of the address decoder 23; 57 and 58 - the signals at the outputs of the flip-flops 42 and 43, respectively; 59 and 60 are the signals at the second and third outputs of the control register 40. respectively; 61 - the signal at the input of the record register 26 operations; 62 and 63 - the signals at the counting inputs of the addition of counters 18 and 19 addresses with

o

0

five

five

responsibly; 64 and 65 are the signals at the write-read control inputs of memory blocks 14 and 15, respectively; 66 is the signal at the control input of the address multiplexer 22; 67 - signal at the output of the comparison unit 21. The computer works as follows. To bring the computer back to its initial state, a reset signal is applied to the reset input 5, as a result of which registers 26, 27 and 40, triggers 41-43 are set to zero.

A series of pulses is applied to the inputs 6 and 7 of the synchronization of the computer.

The operation of a computer is based on the execution of programs (set of commands) stored in block 2 of memory. In turn, each cycle of the operation is completed within several cycles. The duration of the clock is determined by the pulse following period 48. The processor 1 performs the tact-like execution of instructions at the microcommand level.

Consider the operation of a computer with regard to node 4. Figure 6 shows a task queue, represented as a two-way reverse list. Each item in the list contains certain fields that are used when performing procedures with lists. The Forward parameter field and the Back parameter field indicate the starting addresses respectively of the following

5 and the previous list items. Figure 6 (for clarity) in these fields indicates the numbers of the corresponding list items. Field parameter Back the first item in the list

0 is equal to O, and, respectively, equal to

zero the Forward parameter field of the last item in the list.

In addition, various informational gender, for example, their priority

5 and others may be used to perform list operations.

Any list operation is performed in the following order. The main program (the program of the operating system) forms in the operational area of block 2 of memory a block of list parameters.

The structure and format of this block are given in Table 1.

Thereafter, to indicate node 4 o, the need to perform an operation with lists of data in the main program provides for

51

vsod commands The processor 1 proceeds to the execution of this command (Fig. 3). To simplify the execution of this command (Fig. 3) is shown only functionally. On the address bus, processor 1 sets the node address 4

from the addresses of the input-reserved devices behind node 4) the data bus 1 processor causes

(one water,

On

the address of the list parameter block (its location in memory block 2). When the processor 1 receives the signal 53, the address decoder 23 generates the signal 56.

Up to this point in time, node 4 is in the passive mode, waiting for a single value of the 56 signal — the Start signal. With a single signal 56, the address of the parameter block of the list is written into the counter 19 of the address. From the microinstructions memory unit 25, the first microinstruction of the active mode of operation of the node 4 is read.

The micro-command format is shown in Table 2.

In the address field, the address of the following microcommand is set. The low-order field of the address goes from the third output of the microinstructions memory block 25 to the first information input of the multiplexer 28. The rest of the address floor comes from the first output of the microcommands memory 25 to the information input (without the low-order bits) of register 27.

The transition field enters from the second output of the micro-command memory block 25 to the control input of the condition multiplexer 28.

The fields of receivers 1 and 2 contain the number of the component (the register of the counter or trigger), where the corresponding operand should be entered in this microcommand or where the control action should be entered.

The floors of receivers 1 and 2 come from the fourth and fifth outputs of block 25 to the control inputs of the decoders 29 and 30, respectively. The source field contains the number of the bus switch or driver, which, in this microcommand, provides information to the data bus.

The source share is fed to the control input of the decoder 31.

In the address field of the operand and in the address field of the parameter, the addresses

0

five

five

0

0

five

0

five

0

five

operands and parameters contained in memory blocks 15 and 14, respectively.

The control field contains codes used for controlling signals. The control field enters the information input of the control register 40.

The state bit represents the result of performing operations on lists. The status bit enters trigger input 41.

On the timing diagram (Fig.3-6) of the node 4 processing lists for the execution of algorithms of operations (table.4, 6 and 7) are marked in Arabic numerals (each step corresponds to the execution of a specific micro-command). The duration of a cycle is determined by the pulse repetition period 48.

A pulse from the output of the decoder 30 sets up a capture trigger 42 (signal 57). The node 4 goes into standby mode for a single value of the signal 54. After completing the execution of the next cycle of operation, the processor 1 analyzes the state of the signal 57 at the capture input. ; At a single value of the signal 57, the processor 1 generates a signal 54 and goes into the standby mode (the mode of expectation or zero signal 57) and releases the address bus, the data bus and the control bus. At the same time, the bus drivers 36 - 38 are opened by a single signal 54. The address from the output of the counter 19 of the address goes through the multiplexer 22 to the address bus.

By the single signal 60 and, accordingly, the signal 51 from the memory block 2 is read the first word of the list parameter block (operation code) and the signal 61 is written to the operation register 26. Up to the code in register 26 of the microinstructions memory block 25, the first microcommand for performing the required operation is determined;

The list of operations on the lists performed by block 4 is presented in Table 3.

At the beginning of the operation of the computer, the first operation performed by block 4 is Initialization. The parameter block from the list for this operation does not contain 1, 2, and 3-word (ta6l, 1). The words 4 through 8 for each specific list structure have constant meanings. Before working with the lists when performing the Initialization operation, these constants (as well as the constant 00, word 9) are entered into the parameter memory block 14 (Fig. 3).

Table 4 shows the firmware algorithm for the Initialization operation.

In Table 4 and the following tables with firmware algorithms, the following designations are accepted:

Ri 0,1,2 ... - designation and numbering of the cells of block 14;

Li Of, 2. ,, - the designation and numbering of the cells of the block 15j

t - set to 1 the corresponding signal;

I - setting in О the corresponding signal;

- - forwarding operand;

+1 - adding one to the contents of the counters. The remaining symbols are composed of abbreviated names of computer components and their positional numbers (for example, IR16 - information register 16; CM20 - adder 20, etc.). Each line in the algorithm corresponds to a certain microinstruction.

Signal 63 recalculates the address counter 19, signals 60 and 51 read the necessary right and single signal 64 writes to the corresponding cell of block 14, the address of which in each clock cycle is determined by the address field of the parameter of the corresponding micro-command. After writing the parameters to block 14, the Initialization operation is completed.

After the completion of each operation, the signal from the output of the decoder 29 is set to zero trigger 42 (signal 57). Node 4 frees up system buses for processor 1.

In the next clock cycle, the signal from the output of the decoder 29 sets the trigger 43 (signal 58) to one, and the status bit defining the termination condition is written to the trigger 41.

given operation. When the operation completes normally, the status bit is zero.

The format of the state bit node 4 is shown in Table 5.

Node 4 enters the standby mode of the next command to perform any operation. With lists.

With a zero signal value of 57, processor 1 sets the signal 54 to zero and goes into active mode. With a single signal 58, the processor 1 generates a signal 55 and transfers to a subroutine for processing the jitter. By the signal 55, a trigger 43 is set to zero. During the processing of the prejudice, the processor 1 clears the status bit from the trigger 41 for analysis (for simplicity, this procedure is not shown in the timing diagram).

Consider performing one of the operations of the 1st group (Table 3), for example, Search for a list item by name.

The list parameter block (Table 1) for this group of operations contains the first 4 words (from the 0th to the 3rd). In the 2nd and 3rd words of the parameter list box, the starting and ending addresses of the location are located in memory block 2 of the information field (reference) that is searched.

Table 6 shows the firmware algorithm for performing the search operation in question.

Figure 4 shows a timing diagram for the implementation of this algorithm.

First, the firmware executions (lines 1-6, Table 10) are used to read the corresponding words of the parameter block of the list from memory block 2 into the corresponding cells of blocks 14 and 15 (word, word).

When executing microinstructions (lines 7 and 8, Table 6), the address of the name of the item being analyzed is determined. This address is determined by. the summation of the starting address of the list item with the constant code of the corresponding offset. Received. The address is sent to the address counter 18. The address counter 19 is sent the address of the reference name that is being searched.

When executing microinstructions (lines 9-12, Table 6), the first word of the real name of the list element and the reference one is read at the corresponding addresses of the counters 18 and 19 of the address. With a zero value of the signal 66, the multiplexer 22 transmits the contents of the counter 19 to its bypass, with a single value of the signal 66, the contents of the counter 18,

When executing a microcommand (the search for a list item by

Table 13, Table 6) compares the first words of the real and reference names. When they are equal, the signal 67 is equal to 1, in microinstructions (lines 13 and 14, tab., 6) a check is organized: 5 whether the last word of the analyzed field (in this case, the name) is checked. For this purpose, a comparison of the final data address with the current one is organized (lines 14 and 15, Table 6). When there are 20 inequalities (for the case when the field being analyzed contains more than one word), the signal 67 has a zero value, the firmware returns (on line 9, Table 6) 25 to read and check the next words of the field being analyzed.

With the normal completion of the comparison (line 15, tab., 6), the signal 67 em is a single value ,. ,

In this case O is written to the trigger 41, and the address of the found list element is written to the address counter 19 (line 20, Table 6). This address is taken up by processor 1 in the subroutine processing subroutine after the node execution 4 of the specified operation.

With a negative result of the comparison of real and reference names, signal 67 is equal to O (line 13,) a transition is made to check the name of the next element of the list. To do this, the microinstructions (lines 16 and 17, Table 6) calculate the cell address of memory block 2, in which it contains-- from the starting address of the next list item (Forward parameter),

. When executing a microcommand (line 18, table, 6), the address of the second element of the list is found (instead of the address of the first element of the list).

The microcommand (line 19, table, 6) checks the read address for equality 0. The zero value of the read address indicates that the current list item is the last one. In this case, the trigger is

t5

50

name.

Similarly, other search operations of the 1st group are performed (Table 3).

Table 7 shows the algorithm of the program execution program for group 2 (Table 3). Removing elements from the list.

For this operation, in the first block of the parameter list box, specify the address of the element that needs to be removed from the list.

The essence of the algorithm is as follows. Fig. 7 shows a diagram explaining the essence of the execution of this algorithm. At first, organizing with the read back in block 15 the Back and Forward parameter of the i-ro list item (lines 1-7, tabl, 7), the starting address of the i-ro element is specified in ve 1 of the list parameter list.

Then, the Forward i-ro parameter is written instead of the Forward parameter (i-l) -ro of the list element (lines 8 and 9, Table 7), and the Back parameter of the i-ro list element is written instead of the Back parameter of the 1st) list element. So about the i-th element is excluded from the chain of the list,

Fig. 5 shows the time frame for performing the operation; the item is removed from the list.

Similarly, the level of microinstructions and the rest of the list processing radios can be compiled and programmed (Table 3).

Claims (1)

Formula invented An electronic computational computer (computer) containing a processor, a memory and an input / output unit, the processor’s output output is connected to the memory input blocks of the input-output unit, the processor’s information input / output output is connected to the formation input-output blocks A state state 41 is written 1 (row 21, Table 6). If the address of the next list item is nonzero, node 4 returns to check the next list item. After the execution of microinstructions (line 20 or line 21, Table 6), the execution of the statement is completed. Q, five 0 name. Similarly, other operations of the 1st group are performed (Table 3). Table 7 shows the microprogram algorithm for performing the 2nd group operation (Table 3). Deleting an element from the list. For this operation, in the first word of the list of parameters of the list indicates - with the address of the element to be removed from the list. The essence of the algorithm is as follows. Fig. 7 is a diagram explaining the nature of the implementation of this algorithm. At first, reading in the block 15 of the Back and Forward parameters of the list element i-ro (lines 1-7, tabl, 7) is organized. The starting address of the i-element of the element is specified in word 1 of the list parameter block. Then the Forward parameter of the i-ro element is written instead of the Forward parameter (il) -ro of the list item (lines 8 and 9, Table 7), and the Back parameter of the i-ro element of the list is written instead of the Back parameter (i + +1) -th element of the list . Thus, the i-th element is excluded from the chain of the list, Fig. 5 is a time diagram of the operation for removing an item from the list. Similarly, they can be compiled and programmed at the microinstruction level and the rest of the list processing operations (Table 1), Invention Formula An electronic computer (computer) containing a processor, a memory unit and an input / output unit, the processor’s output output is connected to the address inputs of the memory unit and the input / output unit, the information input-output processor is connected to the information inputs / outputs of the unit. the memory and the I / O unit, the read control output from the memory and the write control output to the processor memory are connected respectively to the read input and the block write input, the input control output and the output control output of the processor are connected respectively to the input reading and entry entry block input-; The Q input-output of the processor, the second output, the information output and the input of which are connected respectively to the information input and output of the computer, the tracking output and the input acknowledgment output of the input-output unit | 5 are connected respectively to the additional computer codes, the output acknowledgment input and the tracking input. the input of the I / O unit is connected respectively to the computer inputs of the same name, the processor reset input is connected to the reset input of the input-output unit and the computer reset input, the processor synchronization input is connected to the input of the computer synchronization, - If, in order to improve the performance of a computer when processing list data structures, it additionally contains a memory block 20 25 the second address decoder is connected to the first input of the second element OR, the output of the operation register is connected to the input of the higher bits of the microinstructor memory block address, the output of the address field of the next microcommand of which is connected to the information input of the high priority micros command address register the microinstruction memory block is connected to the control input of the multiplexer of conditions, the output of which is connected to the information input of the lower bit of the microinstruction address register, the output of which is Not with the entry of the least significant bits of the microcommand memory block address, the low bit of the microcommand address of which is connected to the second information input of the condition multiplexer, the output of the control field of the first receiver of the microcommand memory block is connected to the information input of the first control decoder, outputs from the first the seventh of which is connected respectively to the input of the recording of the register of operations, to the recording input of the first counter of the address, with the counting input of the first counter of the address, to the input of the recording control- reading the parameter memory block, with the first input of the setup into the capture trigger, with the write input of the first information register, with the input of the state trigger trigger and with the installation input into the first failure trigger, the output of the control field of the second receiver of the microcommand memory block is connected to the information the input of the second control decoder, the outputs from the first to the fourth of which are connected respectively to the second input of the first OR element, to the counting input of the second address counter, to the recording input of the second information th register and to an input of setting to 1 the capture trigger, the output of the first OR gate is connected to the input of the second recording parameters, operand memory block, first and second information registers, first and second address counters, adder, comparison block, address multiplexer, first and second address decoders, microcommand memory block, operation register, microinstruction address register, condition multiplexer, first the second and third control descramblers, the first, the second and the third bus switches, the first; output - fifth force mapper, control register, state trigger, capture trigger, interrupt trigger, first and second AND elements, first and second OR elements, and the information inputs of the first and second address decoder are connected to the output of the first bus driver and address output of the processor, gating inputs of the first and second address decoders are connected respectively to the output of the controller and the output of the input control of the processor, the output of the first address decoder is connected to the first, informational input multiplexer conditions and the first input of the first element OR, the first output of the second. the address decoder is connected to the control input of the second bus driver, the output of which is connected to the output of the first bus driver, with the information inputs-outputs of the first, second and third bus switches, with information, inputs of the parameter memory and operation register, with information five 0 five 0 five 0 five 0 five the second address decoder is connected to the first input of the second element OR, the output of the operation register is connected to the input of the higher bits of the microinstructor memory block address, the output of the address field of the next microcommand of which is connected to the information input of the high priority micros command address register the microinstruction memory block is connected to the control input of the multiplexer of conditions, the output of which is connected to the information input of the lower bit of the microinstruction address register, the output of which is Not with the entry of the least significant bits of the microcommand memory block address, the low bit of the microcommand address of which is connected to the second information input of the condition multiplexer, the output of the control field of the first receiver of the microcommand memory block is connected to the information input of the first control decoder, outputs from the first the seventh of which is connected respectively to the input of the recording of the register of operations, to the recording input of the first counter of the address, with the counting input of the first counter of the address, to the input of the recording control- reading the parameter memory block, with the first input of the setup into the capture trigger, with the write input of the first information register, with the input of the state trigger trigger and with the installation input into the first failure trigger, the output of the control field of the second receiver of the microcommand memory block is connected to the information the input of the second control decoder, the outputs from the first to the fourth of which are connected respectively to the second input of the first OR element, to the counting input of the second address counter, to the recording input of the second information th register and to an input of setting to 1 the capture trigger, the output of the first OR gate is connected to the input of the second recording the address counter, the output of the comparison block with the third information input of the multiplexer of conditions, the output of the control field of the source of information of the microcommand memory block — with the information of the 6th third control decoder, the codes from the first to the fourth of which are connected respectively to the control inputs of the first and the second bus switch, with the control input of the third bus driver, with the second input of the second OR element, the code of which is connected to the control input of the third bus switch, the field outputs a The memory of the operand memory block and the microinstructor memory block parameter block are connected to the address inputs of the operand memory block and the parameter memory block, respectively, and the output of the microprogram memory block microprogram sign is connected to the information input of the state trigger, the output of which yen with information input of the second bus driver, information input and output of the memory block of operands are connected respectively to information outputs and input of the second bus switch, output of the block Parameter memory is connected to the information input of the second information register, the output of which is connected to the first information inputs of the comparison and adder unit, the output of the first bus switch is connected to the information input of the first information register, the output of which is connected to the information input of the first bus switch and to the second information inputs of the comparison and adder unit, the output of the adder is connected to the information inputs of the third bus driver and the first address counter, D of which is connected to the first information input of the address multiplexer, the output of which is connected to the information input of the first bus driver, the second information input of the address multiplexer is connected to the output of the second address counter and. With the information input of the third bus switch, the output of which is connected to the information input of the second address counter, the output of the field for setting the mode of the microcommand memory block is connected to the information input of the control register, the first, second and third outputs of which are connected respectively to the control input, the address multiplexer, with the information inputs of the fourth and fifth bus drivers, the input of the register of the address of the microinstructions is connected. with the gate inputs of the first and second control decoders, with the first inputs of the first and second elements And with the second synchronization input of the computer, the second inputs of the second and first elements And are connected respectively to the outputs of the control fields of the microinstructions memory block, the outputs of the first and second elements I are connected respectively to the write input of the control register and to the input of the read-behind control. the memory block of the operands, the installation input in the O register of microinstructions is connected to the inputs of the installation in the O register of operations of the control register state trigger, with the second inputs of the installation in the O triggers of the capture and stop and the inputs of the computer reset, the outputs of the triggers of the capture and interrupts connected, respectively, to the inputs of the capture and processor interruption, the output of the confirmation of the capture of which is connected to the fourth information input of the multiplexer of conditions and to the control inputs of the first, fourth, and fifth bus components STUDIO yield acknowledgment ryuani pre- processor connected to the first input for setting a trigger prertani ON, outputs of the fourth and fifth bus drivers - accordingly to the control output. write to memory and with the output of reading control from the processor memory. Table 1 Control word (opcode) The starting address of the first list item Data start address 15 j520533 6 Continuation of table 1 3 End data address 4The parameter offset code Forward 5 parameter offset code; Back 6 Element / list name offset code 7List of priority of the list item 8The offset code of the information field of the list item : h 9 Null constant 00 Note: In the second word, the Starting Data Address indicates the starting address of the data set (reference) in case of search operations п multiplication (Table 2), as well as the data set to be written to the list item (group of operations 3, tabi2). The third word indicates, respectively, the final address of the data array. The offset codes specified in words 4-8 are intended to determine the starting addresses of the corresponding fields of the list elements. The format of the list parameter block is shown in general form. For various operations, individual words in the list parameter block may be skipped. Ta Microcommand Polb first Field Field Field Field of field Field | Field address of the destination address of the receiver Office of the address address panic of the opera meter 1 2 yes specific gender: by name by priority on the information field Move.elements list: deletion the introduction R Bit sos.- neither Table3 17 1H 108 2БП2- ЕО; + 1 NAV 19; 4,108 t 108  + 1 NAV 19; 4108 i 108  + 1 NAV 19: 108 I08  + 1 SCH19; I09 t 109  + 1 SCH19; 108  108  + 1 SCH19; 4108 Bit number Value 1520533 18 Continuation of table 3 Backfilling of the word 4 blocks of the list parameters in the zero cell of the block 14 Word 5 in the first cell of block 14 Word 6 to the second cell of block 14 Word 7 in the third cell of block 14 Word 8 in the fourth cell of block 14 Word 9 in the seventh cell of block 14 T a b e c i 5 O 0 - list item found 1- list item not found nineteen 1tl08 2БП2- лО; 108 3LO-HP16; RMHP17; 4CM20-C4A18; fl08; RO-HP17; 5 |. I08; CM20-C4Ai8; 6,108; L1-HP16; 7БП2- Ь2; (108; CM20-NAV 8 8f 107; R1-HPI7; 9 (107; Ь2-ИР17; 152053320 Table 6 Table Word 1 - LO Word 5 - L1 Word 4 - L2 10CM20-SCA18; 11f 107; 12 4 107  Continuation of table 7 Phie Saffcf o / napar emp , Back af) c f4emp „Bftepea a ovff / FIG. five eight