SU1282141A1 - Buffer storage - Google Patents

Description

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The invention relates to computing and is intended for use in cases where information from the output of the buffer memory device must be read in the same order in which it arrives at the input.

The purpose of the invention is to increase the reliability and speed of the device.

The drawing shows a block diagram of a buffer storage device.

The device contains registers 1, data switch 2, write control blocks 3, decoder 4, first 5 and second 6 counters, address switch 7, OR element 8 and pulse generator 9.

Switch 7 contains AND 10 and 11 elements (in each category), OR element 12 and NOT element 13.

Switch 2 contains the elements And 14 and the element OR 15.

One of the bits in each register 1 is used as a marker. As blocks 3 can be used elements I.

The device works as follows.

Recorded information in the form of a parallel code goes to the inputs of all registers 1. When a pulse appears at the input, the device connects the outputs of counter 5 through switch 7 to the inputs of the decoder 4, which supplies the enabling potential to the corresponding block 3. The input word is written to the corresponding register 1, the marker bit of which is set to 1.

The appearance of a pulse at the input. Reading a device indicates that information has been collected from switch 2 and information from the next register 1 needs to be extracted. This pulse, passed through the OR element 8 and the corresponding block 3, will write O to the corresponding bit of the corresponding register 1. This About through the switch 2 is fed to the input of the driver 9 and unlocks it.

A continuous sequence of pulses from the output of the imaging unit 9 is fed to the counting input of counter 6, which counts until

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register 1, having 1 in the marker bit, is not connected to switch 2. At the same time, the former 9 will be locked.

If the information is recorded in several registers 1, then with the arrival of a read pulse, only one pulse is output at the output of the imaging unit 9.

If there is no information in registers 1, then shaper 9 generates a continuous sequence of pulses.

Thus, the information entering the device is written to registers 1, and the output of the device is received in the same sequence as the input.

Claims (1)

Invention Formula A buffer memory containing registers, first and second counters, recording control blocks whose outputs are connected to the control inputs of the respective registers, pulse generator and an OR element, characterized in that, in order to improve the reliability and speed of the device, an address switch, a decoder and a data switch, the information inputs of which are connected to the outputs of registers, one of the outputs is connected to the input of a pulse shaper, the output of which is connected to the counting input of The counter, the data switch outputs are device outputs, the address switch outputs are connected via a decoder to the data switch control inputs and the first inputs of the write control blocks, the second inputs of which are connected to the output of the OR element, the first input of which is the count input of the first counter and the control the input of the address switch is the write input of the device whose read input is the second input of the OR element, the counter outputs are connected to the information inputs of the address switch, Discount porazr registers inputs connected bottom and are data inputs va ma. Circulation 670 Subscription