SU1363225A2 - Information-input device - Google Patents

Abstract

The invention relates to a cleaning technique and can be used as a device for selecting information channels in multi-channel systems for collecting, recording and processing information. The aim of the invention is to increase the reliability of the device. This goal is achieved by introducing a reversible counter, additional AND elements, and NAND elements, a pulse shaper, which allow timely detection of failures arising during operation. 3 il. .28 P 42I 3/5 iyi-WlgV4 & - G (L oo 05 ooo you ate to Fig. I

Description

The invention relates to computing and can be used as a device for selecting information channels in multi-channel systems for collecting, recording and processing information.

The purpose of the invention is to increase the reliability of the device.

FIG. 1 shows a block diagram of the proposed device; in fig. 2 is a block diagram of a memory unit; in fig. 3 - block diagram of the block delay elements.

The device contains the first register 1, information inputs 2, the second register 3, information outputs 4, the first synchronization input 5, the first memory block 6, the switch 7, the second synchronization input 8, the first 9, the second 10, the third 11 And elements, the OR element 12, the block 13 of the delay elements, the control output 14, the second 15 and the third 16 memory blocks, the first 17 elements NAND, the fourth element 18 AND, the fourth 19, the fifth 20 elements NAND, trigger 21, Fifth 22 and the sixth 23 elements And, the second 24 and the third 25 elements AND-NOT, the address inputs 26, the first installation input 27, the third synchronous input 28, the second is set The input input 29, the second 30 and the first 31 control are usable, the inputs are NOT 32, the seventh 33 and the eighth are 34 AND elements, the reversible counter 35, the former 36, the ninth 37, the tenth 38 and the eleventh 39 elements AND, the second element OR 40, the sixth element AND-NOT 41, the output 42 of the error signal.

Each of blocks 6,. 15 and 16 of the memory consists of the counter 43 of the address, the element AND 44, the driver 45 and the element 46 of the memory.

Block 13 of the delay elements contains the element 47-49 delay, the element is NOT 50 and the element 51 of the delay.

The device works as follows.

Before the start of operation, the signal at input 29 of the installation performs zeroing at all addresses of blocks 6, 15 and 16, as well as setting the reversible counter 35 to zero. To zero memory blocks, a high level of the signal at input 29 permits the passage of clock pulses from input 28 through the AND-NE element 17 to the input of the modification of the address of block 6 and through the elements of AND 22 and 23 to the inputs of the blocks 15 and 16, respectively, of the memory. The low level of the signal at the input of the modification of the address of the memory block, through the AND element 44, records the zero bit to the memory block 46 at the address stored on the address counter 43. On the positive signal differential at the input of the address modification, the unit is added to the contents of the address counter 43. Write zero bits for others

the addresses of memory unit 46 are made similarly.

The device has two modes of operation: the mode of the initial loading of the block 6 and the mode of sampling the data of the measuring channels for processing.

In the bootstrap mode, an entry is made to block 6 of the extraction program. At the same time, input 27 is supplied

high signal level, indicating that the initial loading is in progress, and providing connection of address inputs 26 through switch 7 to information inputs of counter 43 of block address 6. Address inputs 26, accompanied by a low level signal at input 8 of clock pulses, receive address codes of element 46 memories used to write single data bits. Low input signal 8 clock pulses, pass

through the element 18, enters the input of the record of the address of the block 6 and provides the recording of the address code from the address inputs 26 to the counter 43 of the address. On the positive edge of the signal at the input of 8 clock pulses, the shaper 45 generates a low level pulse signal that passes through AND 44 and records a single bit in 46 memories at the address stored at the outputs of the address counter 43. Similarly, single bits are recorded at other addresses supplied to inputs 36 accompanied by a signal on synchronous input 8. Writing a single bit at the K-th address in block 6 means selecting the data of the measuring channel with the K-th address sign in the mode of sampling the data of the measuring channels for processing . At the end of the initial loading at input 27 a low signal level is established.

In the mode of sampling data measuring channels for processing the device operates as follows.

The operation of the device in this mode is controlled by signals at the outputs 30 and 31 of the device. The signals to these inputs (high levels) are received alternately and determine the calibration mode and the measurement mode of the measurement sensors, respectively.

Consider the operation of the device in the measurement mode.

On the leading edge of the signal at input 31, the shaper 36 generates a pulse signal that passes through the delay element 51 and confirms the zero state of the reversible counter 35 through the OR 40 element. A low signal level at the output of the NAND 41 element blocks the signal from passing through the AND element 39. Thereafter, with the advent of the information package.

to device 2, accompanied by a pulse on input 5, on the leading edge of the tracking pulse, data from input 2 is copied to register 1. After the recording is finished, the address part of the message goes through the switch 7 to the information inputs of the address counter 43. The code of the address part of the message is written to the counter 43 of the block 6 by a low level signal at the third output of block 13, which passed the AND 18 element. The high level of the signal at the input of the operation code of the block 6 through the serially connected driver 45 and the And 44 element sets the block memory 46 6 reading mode. The data bit from the memory element 46 is read at the address stored on the address counter 43. The signal at the first output of the block 13 gates the AND 9 element. In the case of reading a single bit of data from the block 6 and with a high signal level at the input 31 of the device, the output of the AND 9 element is a signal that passes the element OR 12, rewrites the contents of the register 1 to register 3. The signal from the output of the OR 12 element is fed to the second input of block 13, where it is held for the time required to write data to the register 3. The signal at the second output of block 13 indicates that the data at outputs 4 of the device are ready. At the same time, the signal from the output of the element OR 12 through the open element And 37 enters the input of the direct count of the counter 35 and adds to its content a unit. The signal at the output of block 13 gates the AND-HEY elements 19 and 20. Depending on the state of the trigger 21, at the output of the IS-HEY element 19 and 20 a low signal level appears. Assuming that the flip-flop 21 is set to one, then a low signal level appears at the output of the NAND element 19. This signal records the address part of the message into the address block 43 of the block 15. By a positive signal differential at the input of the operation code of block 15, i.e., at the output of the AND 33 element, the block shaper 45 forms a low level signal that passes the AND 44 element and writes the unit data bit to the memory element 46 at the address stored on the counter 43, the address of block 15. The processing of subsequent information parcels by the device in this mode is carried out similarly. Thus, at the end of the measurement mode in the memory element 46 of block 15, single bits are recorded at the addresses uniquely corresponding to the address parts of the information packages that were selected for processing in the measurement mode, and the counter 35 records the total number of information words issued to processing in measurement mode.

Consider the operation of the device in the mode of calibration signals input to the device.

In this mode, a low signal level is present at the input 31 of the device, and a high level signal is received at the input 30. The low level at the input 31 blocks the operation of the And 9 element and, consequently, the block 6. The high level of the signal at input 30 and the high level of the signal at the forward output of the trigger 21 allow handling the data read operation from block 15. The low signal level at the inverse output trigger 21 blocks the operation of element 11, i.e., it prohibits reading data from block 16. With the arrival of the information parcel at input 2 of the device accompanied by a low level pulse on input 5 on the leading edge of the tracking pulse, the data from input 2 is copied to the register Tr 1. At the end of the recording, the address part of the message arrives at the information inputs of the counter 43 of the block 15 address. A signal at the fourth output of the block 13 through the open element IS-NOT 19 records the code.address part of the message into the counter 43 of the block 15 address. signal at the first output of block 13 and when reading from block 15 of a single bit at the output of the element And 10, and therefore, at the output of the element OR 12, a signal appears that rewrites the contents of register 1 into register 3. At the outputs 4 of the device, there is data to be issued for processing, accompanied by a ready signal at the output 14 of the device. Simultaneously, the signal at the output of the element OR 12 through the open element And 38 is fed to the input of the countdown of the counter 35 and the unit decreases its content. The processing of subsequent information packages is carried out in a similar way.

High levels of signals at the direct output of the trigger 21 and the output of the NOT 32 element allow the passage of clock pulses from the input 28 through the serially connected elements AND 25 and the element 23 to the input of the block 16 address modification. Under the influence of these clock signals, zero bits are recorded at all addresses of memory unit 46 of block 16. At the end of the calibration mode, a low signal level is established at input 30 of the device. Thus, in the calibration mode, the device issues for processing the values of the calibration signals only those measuring channels that were present in the previous cycle of the measurement mode.

When a high level signal arrives at the device input 31 in the next measurement cycle, the feed edge 36 forms a pulse on the leading edge of the signal

polling the element AND 39. If the output of the element IS-HE 41 at this moment is a low signal level (the counter 35 is in the zero state), then a fault signal does not appear at the output 42 of the device. Otherwise, a signal appears at output 42 indicating a malfunction of the device, since a different number of information words were entered into the processing system in measurement and calibration modes. In addition, when a high level signal arrives at the device input 31 in the next measurement cycle, the selection of information for processing is performed according to the allocation program stored in block 6, trigger 21 changes the state to opposite, unit 16 records single bits at addresses that match with the addresses of the measuring channels, the data from which were issued for processing in this cycle of the measurement mode. At the same time, zero data bits are written to all addresses of block 15, preparing it for operation in the next cycle of the measurement mode.

The technical and economic advantages of the proposed solution are that the introduction of hardware performance control improves the reliability of the device, as it contributes to the timely detection and elimination of failures that occur during operation.

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Claims (1)

Invention Formula Device for entering information on the author. St. No. 1290337, characterized in that, in order to increase the reliability of the device, a reversible counter, a pulse shaper, a second element OR, the ninth, tenth and eleventh elements AND, a sixth element and NAND, a sum.muting and subtracting the inputs of the reversible counter are connected to the outputs of the ninth and tenth elements And, the first inputs of which are connected to the output of the first element OR, the second input of the ninth element And connected to the input of the pulse former and connected to the first control input of the device, the second input of the tenth element nta AND is connected to the second control input of the device, the output of the pulse shaper is connected to the first input of the eleventh element AND 0 and an additional input of a block of delay elements, an additional output of which is connected to the first input of the second OR element, the second input of which is connected to the second installation input of the device, the output of the OR element is connected to the installation input of the reversible counter, the outputs of which are connected to the inputs of the sixth AND-NOT element The output of which is connected to the second input of the eleventh AND element, the output of which is the output of the device error signal. Editor L. Pcholinska Order 5966/41 Compiled by O. Karnova Tehred I. VeresKorrektor I. Muska Circulation 671 Subscription VNIIPI USSR State Committee for Inventions and Discoveries 1 13035, Moscow, W - 35. Raushsk nab., 4/5 Production and printing inception, Uzhgorod, st. Project, 4