SU1287167A1 - Interface for linking two processors via common memory - Google Patents

Abstract

The invention relates to the field of computer technology and is intended for interfacing processors through shared memory in microprocessor systems. The implementation of the device requires a small amount of hardware due to the appropriate construction of synchronization circuits. The device contains an operating memory unit 1, an address multiplexer 2, a register 3, a synchronization unit 4, a trigger 5, an element 6 and a bi-directional bus driver 7. A system processor and a video controller 8 can be used as adjoining processors, in this case the block 4 design simplified. The video controller 8 is addressed in block 1 after sampling at a frequency twice as large as necessary to maintain the desired video output rate by the video controller 8. This eliminates exchange conflicts and ensures high image quality while maintaining the speed of the system processor. 2 Il. // C3f, CSLC32 o f (L with

Description

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The invention relates to computing and can be used to interface a processor with a video controller in a micro-computer with a large information content of the displayed information.

The aim of the invention is to simplify the device.

Figure 1 shows the functional diagram of the device and an example of its connection to the video controller; figure 2 - timing charts of the synchronization unit.

The device (Figo) contains a block

1 operative memory, multiplexer

2 addresses, register 3, synchronization unit 4, trigger 5, element 6, bi-directional bus driver 7. Video controller 8 is connected to the device via inputs 9 and 10 of data and addresses and input 11 of the synchronous request

 access from the second processor. The processor is connected to the device via data input / output 12, input. The 13 addresses and the input 14 of the access asnn1 request from the first processor As the second processor can be used video controller KR 580VG75,

Under the memory access is meant both the read cycle and the write cycle of the memory.

The device works as follows.

The video controller 8 assigns the address to the multiplexer 2. The multiplexer 2 supplies to block 1 either the processor address or the video controller address. The source address switch is triggered by trigger 5, which receives an asynchronous processor access request signal. Block 4 provides the formation of control signals of the block

1 with double frequency. In the absence of an access signal from the processor, the address from the video controller 8 enters block 1, from where information is retrieved for the video controller 8 and stored in register 3. Video controller 8 receives data at a display frequency on the indicator screen. Upon receipt of an asynchronous access signal from the processor multiplexer

2produces the address from the input

13 addresses to block 1, blocking by the element And 6, recording the information selected from block 1 to the register 3. In this case, two

directional bus driver 7 and selected from block 1, the information is fed to the input and output of the processor data 12. Thus, for one clock of reading information from block 1 of the RAM, video controller 8 takes two cycles. To block 1, and in the absence of access to the QT processor’s video files, a double (duplicate) recording of information occurs in register 3. When in one of the During these two clock cycles, the processor accesses block 1, blocking the record in register 3 allows you to store the correct information for fetching video controller 8.

In this way, a conflict-free exchange through the memory is organized with the help of minor hardware costs.

Claims (1)

Invention Formula A device for interfacing two processors through a shared memory containing a main memory unit, an address multiplexer, a register, an And element, a synchronization unit and a trigger whose information input is the input of an asynchronous access request from the first processor of the device, the first and second information inputs of the multiplexer the addresses are the address inputs from the first and second processors of the device, respectively 5 to the address input of the operational memory block, the output of which is connected to the informational input of the register, the output of which is the data output to the second processor of the device, the clock input of the synchronization unit is the input of the request for synchronous access from the second processor of the device, which differs that, in order to simplify the device, a bidirectional bus driver was introduced into it, the first information input / output of which is the input-output data from the first processor of the device, the second information input-output The unidirectional bus driver is connected to the output and information input of the RAM block, the write-read control input of which is connected to the first output of the synchronization block, the second output of which is connected to the first 0 five 3-.12871674 input of the And element and to the input of the synchro bus driver and to the trigger triggering, the inverse output to which of the input of the And element, the output of which is connected to the control input terminal to the synchronization input of the address multiplexer and bidirectional gistra. pinpll Otv g51 C52 P From to 5.6 J Cf (Qm li Ki Jw II FIG. 2