SU1580375A1 - Device for addressing memory units - Google Patents

Abstract

The invention relates to automation and computing and can be used in the manufacture of standard memory cards based on partially usable crystals. The aim of the invention is to expand the field of application and simplify the device by reducing the number of IC packages involved in organizing a continuous address field in standard memory cards based on partially usable crystals. The device can operate in the mode of assigning conditional continuous addresses to a usable memory block and in the mode of accessing usable memory blocks. 1 il.

Description

The invention relates to automation and computer technology and can be applied to address memory blocks in standard boards based on partially usable crystals.

The aim of the invention is to expand the field of application and simplify the device by reducing the number of IC packages involved in organizing a continuous address field in standard memory cards based on partially usable crystals.

The drawing shows a functional diagram of the device for addressing memory blocks.

The device contains counters 1 and 2, a RAM block 3, a memory system 4, a device reset input 5, a clocked device input b, a device write / read input 7, a device setting flag input 8, an address output 9 and a device input 10, Input 11 of the device operation mode.

The device can operate in the mode of assigning conditional continuous addresses to operable blocks — submatrices of the system 4 memory and in the mode of accessing the blocks of the system 4 memory.

The mode of assigning conditional continuous addresses to healthy memory blocks is as follows.

The signal Reset from the input 5 of the device sets the initial state of the counters 1 and 2,

A control signal is supplied to the input 11 of the device operation mode, which is fed to the control inputs of counters 1 and 2 and removes the third state, the device address input 10 is set to the third state in the monitoring mode.

The input of the counter 1 receives a clock pulse from the input 6 of the device and sets the first address of access to the system 4 of the memory, which is received (L

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From the address inputs 9 of the memory system vi, the first block, the submatrix, is energized.

If the unit is operational, after the control is completed, the input signal of the first unit of the memory system 4 is sent to the input of the counter 2, the device receives the first address of the valid block. This information goes to the address inputs of the memory unit 3, and its control inputs from the input 7 of the device's read- write come in the synchronic signal of the write to the 3-unit and record information from counter 2 at the address from the counter. ka 1.

In the event that the first block is not valid, the recording to the memory block 3 is not performed, and the next second clock pulse arrives at the device input 6, which increases the contents of counter 1 by one, and the control of the second memory block 4 of the memory starts,

If the second block is operational (and the first one is not), then at the end of the monitoring, the second unit’s validity signal is sent to the input of counter 2 from the device’s input 8, which sets information about the first valid block at the output of counter 2, This information is sent to the address inputs of the unit 3 memories, and the write-read inputs 7 receive sync signals (write signal + sync pulse) to memory block 3 and the first address from counter 2 records information from the counter (code of the checked block). Thus, at the first address in memory block 3, the physical address of the first valid block of the system 4 memory is recorded, at the second address - the second block, etc.

When the control of the last memory block is completed, the memory block 3 stores the sequence of address codes of valid blocks of the system 4 memory, i.e. it stores the i-th address in memory block 3

from the j-th code (address) of the j-ro suitable block of the system 4 memory,

In the mode of accessing suitable blocks of the system 4 memory from the input 11 of the operation mode of the device, the Monitoring signal is removed and the counters 1 and 2 are set to the third state.

Address address 10 of the device receives the current address of the appeal. Synchronization of readout signals (readout + sync pulse) is fed to the input 7 of the device. The i-th logical address from block 3 reads the j-th physical address of a usable memory system block, which from address output 9 of the device goes to the address input of memory system 4 and excites the j-th year block. a valid block is determined by the read time from memory block 3.

Claims (1)

Invention Formula A device for addressing blocks of memory containing first and second counters and a block of RAM, about a tla and partly so that, in order to expand the area of application and simplify the device by reducing the number of cases of microcircuits in standard boards based on partially usable chips , the reset input of the device is connected to the reset inputs of the first and second counters, the clocked input of the device is connected to the counting input of the first counter, the write-read input of the device is connected to the control input of the main memory unit, the device operation mode is connected to the control inputs of the first and second counters; the installation flag of the device’s validity flag is connected to the counting input of the second counter; the address input of the device is connected to the output of the second counter and the address input of the main memory unit; the information output of the main memory unit is connected to the output first counter and address output of the device. 6 o 5 o BUT 7 o L Editor I. Derbak Compiled by A. Barkin Tehred A.Kravchuk Proofreader T.Paly Order 2013 Circulation 565 VNIIPI State Committee for Inventions and Discoveries at the State Committee on Science and Technology (СКНТ С) (СР 113035, Moscow, Ж-35, Raushsk nlb., 4/5 Subscription