SU1522225A1 - Device for interfacing processor with video monitor - Google Patents

Abstract

The invention relates to computing and can be used in microcomputers with a graphic display of high resolution. The aim of the invention is to increase speed and reduce equipment. The device contains an operating memory unit 1, an address multiplexer 2, a register 3, an OR 4 element, a trigger 5, the first, second delay elements 6, 7, the first, second elements AND 8, 9. The device provides for uncontrolled operation of the processor and video controller through a shared memory be 1 il.

Description

The invention relates to computing and can be used in micro computers with a high resolution graphic display.

The aim of the invention is to increase speed and reduce equipment.

The drawing shows the block diagram of the device.

The device contains a block of 1 memory, address multiplexer 2, register 3, element 4 OR, trigger 5, first, second delay elements 6, 7, first, second elements AND 8, 9, input-output 10 of the device for connecting the processor data bus , output 11 of the device for connecting the information input of the video controller, inputs 12 ,. 13 devices for connecting the processor and video controller address outputs, device input 14 for connecting the video controller address synchronization output, device inputs 15, 16 for connecting the processor's read and write outputs, device output 17 for connecting the processor exchange acknowledgment input.

The device works as follows.

The time period of the synchronization signal from input 14 is divided into two cycles T1 and T2. The tact T1 is given to the processor to read (write) information from the RAM unit 1. The tact T2 is given to the video controller to read the displayed information. The video controller reads data from block I of the RAM with the display frequency on the screen of dTopa. Upon request of the synchronous access of the processor, the trigger 5 is set to one state with the onset of the clock T. The signal from input 14 in the T1 cycle multiplexer 2

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: The address transmits the processor's address signal from input 12 to the address inputs of the block; Ka 1 of the RAM. The duration of the signal delay by the delay element 6 is not less than the switching time of the multiplexer 2 addresses and

The time for setting the address at the input of the RAM 1 unit. If the request for asynchronous processor access is intended to record information in the RAM block 1 (a high level signal is set at input 16), then a write pulse is generated at the output of element 8I, the duration of which is determined by the signal delay at delay element 7. The length of the signal delay, the delay element 7, is determined by the time required to write information to the register 3 from the operational memory block 1. During the absence of a write pulse at the output of the element 8, there will be a high level of the signal, according to which from block 1

 RAM will be read information. And if clock 11 is executed and there is an asynchronous processor access request to read information from RAM 1, a high-level read signal is set at input 16), then the read information will be written to register 3 until an output signal appears. 7 delays. In this case, the information from register 3 is output to the rest of the retention time of the readout signal from input 15 to the processor’s data bus. When a signal appears at the output of delay element 7 at output 9, a confirmation signal is generated to the processor for the entire last hold time of the asynchronous access request.

In T2, the address multiplexer 2 transmits to the memory unit 1 signals from the video controller address bus for reading the last displayed information. The main condition for ensuring the operability of the device is to exceed the synchronization signal follow-up period and the duration of two cycles of accessing the first memory block 1.

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Claims (1)

Invention Formula A device for interfacing a processor and a video controller that contains an RAM block, an address multiplexer, the first AND element, a trigger and a register, whose information input is connected to the information output of the RAM block and the device output for connecting the video input of the video controller; the memory is connected to the output of the address multiplexer, the first and second information inputs of which are the inputs of the device for connecting the address outputs respectively the processor A video controller, characterized in that, in order to increase speed and reduce the equipment’s hardware, a second AND element, a first, second delay element, and an OR element, the first input of which is an input for connecting the recording output of the processor and connected to the first input of the first element is AND, the second input of the OR element is connected to the register synchronization input and is the input of the device for connecting the processor readout output, the OR element output is connected to the information input, a trigger a and. with the first input of the second element I, the synchronization input of the ritger and the control input of the address multiplexer are the input of the device for connecting the video output address synchronization output of the video controller, the output of the trigger through the first delay element is connected to the second input of the first And element and to the input of the second delay element the output is joporo connected to the third input of the first element And, to the second input of the second element And and to the input of the register record, the output of the first element And connected to the input of the record-read-. Neither the RAM block, the output of the second element I is the output of the device for connecting the processor exchange acknowledgment input, the register output and the information input of the RAM block are the input-output of the device for connecting the processor's data bus. thirty 35 40 45 50